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69
kernel/include/drivers/irq/arm/gicv2.h
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69
kernel/include/drivers/irq/arm/gicv2.h
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#ifndef _KERNEL_DRIVERS_IRQ_ARM_GICV2_H
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#define _KERNEL_DRIVERS_IRQ_ARM_GICV2_H
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#include <drivers/driver_manager.h>
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#include <drivers/irq/irq_api.h>
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#include <libkern/mask.h>
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#include <libkern/types.h>
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enum GICDControlMasks {
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MASKDEFINE(GICD_ENABLE, 0, 1),
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};
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enum GICCControlMasks {
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MASKDEFINE(GICC_ENABLE_GR1, 0, 1),
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MASKDEFINE(GICC_FIQ_BYP_DIS_GR1, 5, 1),
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MASKDEFINE(GICC_IRQ_BYP_DIS_GR1, 6, 1),
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MASKDEFINE(GICC_EO_IMODE_NS, 9, 1),
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};
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struct gicv2_distributor_registers {
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uint32_t control;
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uint32_t typer;
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uint32_t iidr;
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SKIP(0x008 + 0x4, 0x080);
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uint32_t igroup[8];
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SKIP(0x09C + 0x4, 0x100);
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uint32_t isenabler[8];
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SKIP(0x11C + 0x4, 0x180);
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uint32_t icenabler[8];
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SKIP(0x19C + 0x4, 0x200);
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uint32_t ispendr[8];
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SKIP(0x21C + 0x4, 0x280);
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uint32_t icpendr[8];
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SKIP(0x29C + 0x4, 0x300);
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uint32_t isactiver[8];
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SKIP(0x31C + 0x4, 0x380);
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uint32_t icactiver[8];
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SKIP(0x39C + 0x4, 0x400);
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uint32_t ipriorityr[64];
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SKIP(0x4FC + 0x4, 0x800);
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uint32_t itargetsr[64];
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SKIP(0x8FC + 0x4, 0xC00);
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uint32_t icfgr[16];
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// TO BE CONTINUED
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};
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typedef struct gicv2_distributor_registers gicv2_distributor_registers_t;
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struct gicv2_cpu_interface_registers {
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uint32_t control;
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uint32_t pmr;
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uint32_t bpr;
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uint32_t iar;
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uint32_t eoir;
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uint32_t hppir;
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uint32_t abpr;
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uint32_t aiar;
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uint32_t aeoir;
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uint32_t ahppir;
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// TO BE CONTINUED
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};
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typedef struct gicv2_cpu_interface_registers gicv2_cpu_interface_registers_t;
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void gicv2_enable_irq(irq_line_t id, irq_priority_t prior, irq_flags_t flags, int cpu_mask);
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void gicv2_install();
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void gicv2_install_secondary_cpu();
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uint32_t gicv2_interrupt_descriptor();
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void gicv2_end(uint32_t int_disc);
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#endif //_KERNEL_DRIVERS_IRQ_ARM_GICV2_H
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35
kernel/include/drivers/irq/irq_api.h
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35
kernel/include/drivers/irq/irq_api.h
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#ifndef _KERNEL_DRIVERS_IRQ_IRQ_API_H
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#define _KERNEL_DRIVERS_IRQ_IRQ_API_H
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#include <libkern/types.h>
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// This value shows the maximum number of irqs OS supports. It is irqdev independent,
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// thus irqdev implementations should double check the irqlines.
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#define IRQ_HANDLERS_MAX 256
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#define ALL_CPU_MASK 0xff
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#define BOOT_CPU_MASK 0x01
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typedef int irq_flags_t;
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typedef int irq_line_t;
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typedef uint8_t irq_priority_t;
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typedef void (*irq_handler_t)(irq_line_t line);
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// Currently flags maps to devtree irq_flags.
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// Later we might need to enhance irq_flags_from_devtree() to use as translator.
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#define IRQ_FLAG_EDGE_TRIGGERED (1 << 0)
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struct irqdev_descritptor {
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uint32_t (*interrupt_descriptor)();
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void (*end_interrupt)(uint32_t int_desc);
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void (*enable_irq)(irq_line_t line, irq_priority_t prior, irq_flags_t type, int cpu_mask);
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};
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typedef struct irqdev_descritptor irqdev_descritptor_t;
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static inline irq_flags_t irq_flags_from_devtree(uint32_t devtree_irq_flags) { return (irq_flags_t)devtree_irq_flags; }
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void irq_register_handler(irq_line_t line, irq_priority_t prior, irq_flags_t flags, irq_handler_t func, int cpu_mask);
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void irq_set_dev(irqdev_descritptor_t irqdev_desc);
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irq_line_t irqline_from_id(int id);
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#endif
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12
kernel/include/drivers/irq/riscv/plic.h
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12
kernel/include/drivers/irq/riscv/plic.h
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#ifndef _KERNEL_DRIVERS_IRQ_RISCV_PLIC_H
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#define _KERNEL_DRIVERS_IRQ_RISCV_PLIC_H
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#include <drivers/driver_manager.h>
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#include <drivers/irq/irq_api.h>
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void plic_install();
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void plic_enable_irq(irq_line_t id, irq_priority_t prior, irq_flags_t flags, int cpu_mask);
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uint32_t plic_interrupt_descriptor();
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void plic_end(uint32_t id);
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#endif //_KERNEL_DRIVERS_IRQ_RISCV_PLIC_H
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14
kernel/include/drivers/irq/x86/pic.h
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14
kernel/include/drivers/irq/x86/pic.h
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#ifndef _KERNEL_DRIVERS_IRQ_X86_PIC_H
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#define _KERNEL_DRIVERS_IRQ_X86_PIC_H
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#include <platform/x86/port.h>
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#define MASTER_PIC_CMD 0x0020
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#define MASTER_PIC_DATA 0x0021
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#define SLAVE_PIC_CMD 0x00A0
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#define SLAVE_PIC_DATA 0x00A1
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#define ICW4_8086 0x01
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void pic_remap(unsigned int offset1, unsigned int offset2);
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#endif
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