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Ayaan Tunio
2025-02-12 09:54:05 -05:00
commit 7118adc514
1108 changed files with 80873 additions and 0 deletions
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14
kernel/include/platform/arm32/cpuinfo.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_CPUINFO_H
#define _KERNEL_PLATFORM_ARM32_CPUINFO_H
#include <libkern/c_attrs.h>
#include <libkern/types.h>
#include <platform/generic/cpu.h>
static inline bool cpuinfo_has_1gb_pages()
{
// Only for 64bits.
return false;
}
#endif // _KERNEL_PLATFORM_ARM32_CPUINFO_H

51
kernel/include/platform/arm32/fpu/fpuv4.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_FPU_FPUV4_H
#define _KERNEL_PLATFORM_ARM32_FPU_FPUV4_H
#include <drivers/driver_manager.h>
#include <libkern/mask.h>
#include <libkern/types.h>
#include <platform/arm32/interrupts.h>
#include <platform/arm32/registers.h>
#include <platform/arm32/target/cortex-a15/device_settings.h>
#define FPU_STATE_ALIGNMENT (16)
typedef struct {
uint64_t d[32];
} __attribute__((aligned(FPU_STATE_ALIGNMENT))) fpu_state_t;
void fpuv4_install();
void fpu_init_state(fpu_state_t* new_fpu_state);
extern uint32_t read_fpexc();
extern void write_fpexc(uint32_t);
extern void fpu_save(void*);
extern void fpu_restore(void*);
static inline void fpu_enable()
{
write_fpexc(read_fpexc() | (1 << 30));
}
static inline void fpu_disable()
{
write_fpexc(read_fpexc() & (~(1 << 30)));
}
static inline int fpu_is_avail()
{
return (((read_cpacr() >> 20) & 0b1111) == 0b1111);
}
static inline void fpu_make_avail()
{
write_cpacr(read_cpacr() | ((0b1111) << 20));
}
static inline void fpu_make_unavail()
{
// Simply turn it off to make it unavailble.
uint32_t val = read_cpacr() & (~((0b1111) << 20));
write_cpacr(val | ((0b0101) << 20));
}
#endif //_KERNEL_PLATFORM_ARM32_FPU_FPUV4_H

10
kernel/include/platform/arm32/init.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_INIT_H
#define _KERNEL_PLATFORM_ARM32_INIT_H
#include <libkern/types.h>
void platform_init_boot_cpu();
void platform_setup_boot_cpu();
void platform_setup_secondary_cpu();
#endif /* _KERNEL_PLATFORM_ARM32_INIT_H */

33
kernel/include/platform/arm32/interrupts.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_INTERRUPTS_H
#define _KERNEL_PLATFORM_ARM32_INTERRUPTS_H
#include <drivers/irq/irq_api.h>
#include <libkern/mask.h>
#include <libkern/types.h>
void interrupts_setup();
void interrupts_setup_secondary_cpu();
extern char STACK_ABORT_TOP;
extern char STACK_UNDEFINED_TOP;
extern char STACK_IRQ_TOP;
extern char STACK_SVC_TOP;
extern char STACK_TOP;
extern void swi(uint32_t num);
extern void set_svc_stack(uint32_t stack);
extern void set_irq_stack(uint32_t stack);
extern void set_abort_stack(uint32_t stack);
extern void set_undefined_stack(uint32_t stack);
extern void undefined_handler(trapframe_t* tf);
extern void svc_handler(trapframe_t* tf);
extern void prefetch_abort_handler(trapframe_t* tf);
extern void data_abort_handler(trapframe_t* tf);
extern void irq_handler(trapframe_t* tf);
extern void fast_irq_handler(trapframe_t* tf);
void gic_setup();
void gic_setup_secondary_cpu();
#endif /* _KERNEL_PLATFORM_ARM32_INTERRUPTS_H */

10
kernel/include/platform/arm32/pmm/settings.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_PMM_SETTINGS_H
#define _KERNEL_PLATFORM_ARM32_PMM_SETTINGS_H
#define KERNEL_PM_BASE 0x80100000
#define PMM_BLOCK_SIZE (1024)
#define PMM_BLOCK_SIZE_KB (1)
#define PMM_BLOCKS_PER_BYTE (8)
#endif /* _KERNEL_PLATFORM_ARM32_PMM_SETTINGS_H */

175
kernel/include/platform/arm32/registers.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_REGISTERS_H
#define _KERNEL_PLATFORM_ARM32_REGISTERS_H
#include <libkern/types.h>
#include <platform/arm32/system.h>
static inline uint32_t extract_bits(uint32_t a, int bottom, int top)
{
int diff = top - bottom + 1;
return (a >> bottom) & ((1 << (diff)) - 1);
}
static inline uint32_t read_r3()
{
uint32_t val;
asm volatile("mov %0, r3"
: "=r"(val)
:);
return val;
}
static inline uint32_t read_far()
{
uint32_t val;
asm volatile("mrc p15, 0, %0, c6, c0, 0"
: "=r"(val)
:);
return val;
}
static inline uint32_t read_cbar()
{
uint32_t val;
asm volatile("mrc p15, 4, %0, c15, c0, 0"
: "=r"(val)
:);
return val;
}
static inline uint32_t read_ifsr()
{
uint32_t val;
asm volatile("mrc p15, 0, %0, c5, c0, 1"
: "=r"(val)
:);
return val;
}
static inline uint32_t read_dfsr()
{
uint32_t val;
asm volatile("mrc p15, 0, %0, c5, c0, 0"
: "=r"(val)
:);
return val;
}
static inline uint32_t read_cpsr()
{
uint32_t cpsr;
asm volatile("mrs %0, cpsr"
: "=r"(cpsr)
:);
return cpsr;
}
static inline uint32_t read_spsr()
{
uint32_t spsr;
asm volatile("mrs %0, spsr"
: "=r"(spsr)
:);
return spsr;
}
static inline uint32_t read_cpacr()
{
uint32_t cpacr;
asm volatile("mrc p15, 0, %0, c1, c0, 2"
: "=r"(cpacr)
:);
return cpacr;
}
static inline void write_cpacr(uint32_t val)
{
asm volatile("mcr p15, 0, %0, c1, c0, 2"
:
: "r"(val)
: "memory");
system_instruction_barrier();
}
static inline uint32_t read_nsacr()
{
uint32_t cpacr;
asm volatile("mrc p15, 0, %0, c1, c1, 2"
: "=r"(cpacr)
:);
return cpacr;
}
static inline void write_nsacr(uint32_t val)
{
asm volatile("mcr p15, 0, %0, c1, c1, 2"
:
: "r"(val)
: "memory");
system_instruction_barrier();
}
static inline uint32_t read_hcptr()
{
uint32_t cpacr;
asm volatile("mrc p15, 4, %0, c1, c1, 2"
: "=r"(cpacr)
:);
return cpacr;
}
static inline void write_hcptr(uint32_t val)
{
asm volatile("mcr p15, 4, %0, c1, c1, 2"
:
: "r"(val)
: "memory");
system_instruction_barrier();
}
static inline uint32_t read_cpu_id_register()
{
uint32_t res;
asm volatile("mrc p15, 0, %0, c0, c0, 5"
: "=r"(res)
:);
return res;
}
static inline uint32_t read_midr()
{
uint32_t res;
asm volatile("mrc p15, 0, %0, c0, c0, 0"
: "=r"(res)
:);
return res;
}
static inline uint32_t read_actlr()
{
uint32_t res;
asm volatile("mrc p15, 0, %0, c1, c0, 1"
: "=r"(res)
:);
return res;
}
static inline void write_actlr(uint32_t val)
{
asm volatile("mcr p15, 0, %0, c1, c0, 1"
:
: "r"(val)
: "memory");
system_instruction_barrier();
}
static inline void write_iciallu(uint32_t val)
{
asm volatile("mcr p15, 0, %0, c7, c5, 0"
:
: "r"(val)
: "memory");
system_instruction_barrier();
}
#endif /* _KERNEL_PLATFORM_ARM32_REGISTERS_H */

17
kernel/include/platform/arm32/syscalls/params.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_SYSCALLS_PARAMS_H
#define _KERNEL_PLATFORM_ARM32_SYSCALLS_PARAMS_H
#include <platform/arm32/tasking/trapframe.h>
#define SYSCALL_ID(tf) (tf->r[7])
#define SYSCALL_VAR1(tf) (tf->r[0])
#define SYSCALL_VAR2(tf) (tf->r[1])
#define SYSCALL_VAR3(tf) (tf->r[2])
#define SYSCALL_VAR4(tf) (tf->r[3])
#define SYSCALL_VAR5(tf) (tf->r[4])
#define return_val (tf->r[0])
#define return_with_val(val) \
(return_val = val); \
return
#endif // _KERNEL_PLATFORM_ARM32_SYSCALLS_PARAMS_H

132
kernel/include/platform/arm32/system.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_SYSTEM_H
#define _KERNEL_PLATFORM_ARM32_SYSTEM_H
#include <libkern/c_attrs.h>
#include <libkern/types.h>
/**
* INTS
*/
void system_disable_interrupts();
void system_enable_interrupts();
void system_enable_interrupts_only_counter();
inline static void system_disable_interrupts_no_counter() { asm volatile("cpsid i"); }
inline static void system_enable_interrupts_no_counter() { asm volatile("cpsie i"); }
/**
* PAGING
*/
inline static void system_instruction_barrier()
{
asm volatile("isb");
}
inline static void system_data_synchronise_barrier()
{
asm volatile("dsb ISH");
}
inline static void system_data_memory_barrier()
{
asm volatile("dmb ISH");
}
inline static void system_flush_local_tlb_entry(uintptr_t vaddr)
{
system_data_synchronise_barrier();
asm volatile("mcr p15, 0, %0, c8, c7, 3"
:
: "r"(vaddr)
: "memory");
system_data_synchronise_barrier();
system_instruction_barrier();
}
inline static void system_flush_all_cpus_tlb_entry(uintptr_t vaddr)
{
system_data_synchronise_barrier();
asm volatile("mcr p15, 0, %0, c8, c3, 3"
:
: "r"(vaddr)
: "memory");
system_data_synchronise_barrier();
system_instruction_barrier();
}
inline static void system_flush_whole_tlb()
{
asm volatile("mcr p15, 0, %0, c8, c7, 0"
:
: "r"(0)
: "memory");
system_data_synchronise_barrier();
}
inline static void system_set_pdir(uintptr_t pdir0, uintptr_t pdir1)
{
system_data_synchronise_barrier();
asm volatile("mcr p15, 0, %0, c2, c0, 0"
:
: "r"(pdir0)
: "memory");
system_flush_whole_tlb();
}
inline static void system_enable_write_protect()
{
}
inline static void system_disable_write_protect()
{
}
inline static void system_enable_paging()
{
uint32_t val;
asm volatile("mrc p15, 0, %0, c1, c0, 0"
: "=r"(val));
asm volatile("orr %0, %1, #0x1"
: "=r"(val)
: "r"(val));
asm volatile("mcr p15, 0, %0, c1, c0, 0" ::"r"(val)
: "memory");
system_instruction_barrier();
}
inline static void system_disable_paging()
{
}
inline static void system_stop_until_interrupt()
{
asm volatile("wfi");
}
NORETURN inline static void system_stop()
{
system_disable_interrupts();
system_stop_until_interrupt();
while (1) { }
}
/**
* CPU
*/
void system_cache_clean_and_invalidate(void* addr, size_t size);
void system_cache_invalidate(void* addr, size_t size);
void system_cache_clean(void* addr, size_t size);
inline static int system_cpu_id()
{
// inlined read_cpu_id_register();
uint32_t res;
asm volatile("mrc p15, 0, %0, c0, c0, 5"
: "=r"(res)
:);
return res & 0x3;
}
#endif /* _KERNEL_PLATFORM_ARM32_SYSTEM_H */

43
kernel/include/platform/arm32/target/cortex-a15/device_settings.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TARGET_CORTEX_A15_DEVICE_SETTINGS_H
#define _KERNEL_PLATFORM_ARM32_TARGET_CORTEX_A15_DEVICE_SETTINGS_H
/**
* Used devices:
* uart
* gicv2
* sp804
* pl181
* pl111
* pl050
* pl031
*/
/* Base is read from CBAR */
#define GICv2_DISTRIBUTOR_OFFSET 0x1000
#define GICv2_CPU_INTERFACE_OFFSET 0x2000
#define UART_BASE 0x1c090000
#define SP804_BASE 0x1c110000
#define PL181_BASE 0x1c050000
#define PL111_BASE 0x1c1f0000
#define PL050_KEYBOARD_BASE 0x1c060000
#define PL050_MOUSE_BASE 0x1c070000
#define PL031_BASE 0x1c170000
/**
* Interrupt lines:
* SP804 TIMER1: 2nd line in SPI (32+2)
*/
#define SP804_TIMER1_IRQ_LINE (32 + 2)
#define PL050_KEYBOARD_IRQ_LINE (32 + 12)
#define PL050_MOUSE_IRQ_LINE (32 + 13)
#endif /* _KERNEL_PLATFORM_ARM32_TARGET_CORTEX_A15_DEVICE_SETTINGS_H */

8
kernel/include/platform/arm32/target/cortex-a15/memmap.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TARGET_CORTEX_A15_MEMMAP_H
#define _KERNEL_PLATFORM_ARM32_TARGET_CORTEX_A15_MEMMAP_H
#define KMALLOC_BASE (KERNEL_BASE + 0x400000)
extern struct memory_map* arm_memmap;
#endif /* _KERNEL_PLATFORM_ARM32_TARGET_CORTEX_A15_MEMMAP_H */

6
kernel/include/platform/arm32/target/cpu_part_numbers.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TARGET_CPU_PART_NUMBERS_H
#define _KERNEL_PLATFORM_ARM32_TARGET_CPU_PART_NUMBERS_H
#define PART_NUMBER_CORTEX_A15 (0xC0F)
#endif // _KERNEL_PLATFORM_ARM32_TARGET_CPU_PART_NUMBERS_H

6
kernel/include/platform/arm32/target/general/core_setup.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TARGET_GENERAL_CORE_SETUP_H
#define _KERNEL_PLATFORM_ARM32_TARGET_GENERAL_CORE_SETUP_H
int cortex_a15_setup();
#endif // _KERNEL_PLATFORM_ARM32_TARGET_GENERAL_CORE_SETUP_H

22
kernel/include/platform/arm32/tasking/context.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TASKING_CONTEXT_H
#define _KERNEL_PLATFORM_ARM32_TASKING_CONTEXT_H
#include <libkern/c_attrs.h>
#include <libkern/types.h>
typedef struct {
uint32_t r[9];
uint32_t lr;
} PACKED context_t;
static inline uintptr_t context_get_instruction_pointer(context_t* ctx)
{
return ctx->lr;
}
static inline void context_set_instruction_pointer(context_t* ctx, uintptr_t ip)
{
ctx->lr = ip;
}
#endif // _KERNEL_PLATFORM_ARM32_TASKING_CONTEXT_H

12
kernel/include/platform/arm32/tasking/dump_impl.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TASKING_DUMP_IMPL_H
#define _KERNEL_PLATFORM_ARM32_TASKING_DUMP_IMPL_H
#include <libkern/types.h>
#include <tasking/bits/dump.h>
#include <tasking/tasking.h>
int dump_impl(dump_data_t* data);
int dump_kernel_impl(dump_data_t* dump_data, const char* err_desc);
int dump_kernel_impl_from_tf(dump_data_t* dump_data, const char* err_desc, trapframe_t* tf);
#endif // _KERNEL_PLATFORM_ARM32_TASKING_DUMP_IMPL_H

10
kernel/include/platform/arm32/tasking/signal_impl.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TASKING_SIGNAL_IMPL_H
#define _KERNEL_PLATFORM_ARM32_TASKING_SIGNAL_IMPL_H
#include <libkern/types.h>
struct thread;
int signal_impl_prepare_stack(struct thread* thread, int signo, uintptr_t old_sp, uintptr_t magic);
int signal_impl_restore_stack(struct thread* thread, uintptr_t* old_sp, uintptr_t* magic);
#endif // _KERNEL_PLATFORM_ARM32_TASKING_SIGNAL_IMPL_H

107
kernel/include/platform/arm32/tasking/trapframe.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_TASKING_TRAPFRAME_H
#define _KERNEL_PLATFORM_ARM32_TASKING_TRAPFRAME_H
#include <libkern/c_attrs.h>
#include <libkern/log.h>
#include <libkern/types.h>
#define CPSR_M_USR 0x10U
#define CPSR_M_FIQ 0x11U
#define CPSR_M_IRQ 0x12U
#define CPSR_M_SVC 0x13U
#define CPSR_M_MON 0x16U
#define CPSR_M_ABT 0x17U
#define CPSR_M_HYP 0x1AU
#define CPSR_M_UND 0x1BU
#define CPSR_M_SYS 0x1FU
typedef struct {
uint32_t user_flags;
uint32_t user_sp;
uint32_t user_lr;
uint32_t r[13];
uint32_t user_ip;
} PACKED trapframe_t;
static inline uintptr_t get_stack_pointer(trapframe_t* tf)
{
return tf->user_sp;
}
static inline void set_stack_pointer(trapframe_t* tf, uintptr_t sp)
{
tf->user_sp = sp;
}
static inline uintptr_t get_frame_pointer(trapframe_t* tf)
{
return 0;
}
static inline void set_frame_pointer(trapframe_t* tf, uintptr_t bp)
{
}
static inline uintptr_t get_instruction_pointer(trapframe_t* tf)
{
return tf->user_ip;
}
static inline void set_instruction_pointer(trapframe_t* tf, uintptr_t ip)
{
tf->user_ip = ip;
}
static inline uint32_t get_syscall_result(trapframe_t* tf)
{
return tf->r[0];
}
static inline void set_syscall_result(trapframe_t* tf, uintptr_t val)
{
tf->r[0] = val;
}
/**
* STACK FUNCTIONS
*/
static inline void tf_push_to_stack(trapframe_t* tf, uintptr_t val)
{
tf->user_sp -= sizeof(uintptr_t);
*((uintptr_t*)tf->user_sp) = val;
}
static inline uintptr_t tf_pop_to_stack(trapframe_t* tf)
{
uintptr_t val = *((uintptr_t*)tf->user_sp);
tf->user_sp += sizeof(uintptr_t);
return val;
}
static inline void tf_move_stack_pointer(trapframe_t* tf, int32_t val)
{
tf->user_sp += val;
}
static inline void tf_setup_as_user_thread(trapframe_t* tf)
{
tf->user_flags = 0x60000100 | CPSR_M_USR;
}
static inline void tf_setup_as_kernel_thread(trapframe_t* tf)
{
tf->user_flags = 0x60000100 | CPSR_M_SYS;
}
static void dump_tf(trapframe_t* tf)
{
for (int i = 0; i < 13; i++) {
log("r[%d]: %x", i, tf->r[i]);
}
log("sp: %x", tf->user_sp);
log("ip: %x", tf->user_ip);
log("fl: %x", tf->user_flags);
}
#endif // _KERNEL_PLATFORM_ARM32_TASKING_TRAPFRAME_H

21
kernel/include/platform/arm32/vmm/consts.h Normal file
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#define VMM_LV0_ENTITY_COUNT (256)
#define VMM_LV1_ENTITY_COUNT (4096)
#define VMM_PAGE_SIZE (4096)
#define VMM_OFFSET_IN_DIRECTORY(a) (((a) >> 20) & 0xfff)
#define VMM_OFFSET_IN_TABLE(a) (((a) >> 12) & 0xff)
#define VMM_OFFSET_IN_PAGE(a) ((a)&0xfff)
#define TABLE_START(vaddr) ((vaddr >> 20) << 20)
#define PAGE_START(vaddr) ((vaddr >> 12) << 12)
#define FRAME(addr) (addr / VMM_PAGE_SIZE)
#define PTABLE_TOP_KERNEL_OFFSET 3072
#define PTABLE_LV_TOP (1)
#define PTABLE_LV0_VADDR_OFFSET (12)
#define PTABLE_LV1_VADDR_OFFSET (20)
#define USER_HIGH 0xbfffffff
#define KERNEL_BASE 0xc0000000
#endif //_KERNEL_PLATFORM_ARM32_VMM_CONSTS_H

21
kernel/include/platform/arm32/vmm/mmu.h Normal file
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typedef uint32_t ptable_entity_t;
typedef uint32_t arch_pf_info_t;
ptable_entity_t vm_mmu_to_arch_flags(mmu_flags_t mmu_flags, ptable_lv_t lv);
mmu_flags_t vm_arch_to_mmu_flags(ptable_entity_t* entity, ptable_lv_t lv);
mmu_pf_info_flags_t vm_arch_parse_pf_info(arch_pf_info_t info);
void vm_ptable_entity_set_default_flags(ptable_entity_t* entity, ptable_lv_t lv);
void vm_ptable_entity_allocated(ptable_entity_t* entity, ptable_lv_t lv);
void vm_ptable_entity_invalidate(ptable_entity_t* entity, ptable_lv_t lv);
void vm_ptable_entity_set_mmu_flags(ptable_entity_t* entity, ptable_lv_t lv, mmu_flags_t mmu_flags);
void vm_ptable_entity_rm_mmu_flags(ptable_entity_t* entity, ptable_lv_t lv, mmu_flags_t mmu_flags);
void vm_ptable_entity_set_frame(ptable_entity_t* entity, ptable_lv_t lv, uintptr_t frame);
uintptr_t vm_ptable_entity_get_frame(ptable_entity_t* entity, ptable_lv_t lv);
ptable_state_t vm_ptable_entity_state(ptable_entity_t* entity, ptable_lv_t lv);
bool vm_ptable_entity_is_present(ptable_entity_t* entity, ptable_lv_t lv);
bool vm_ptable_entity_is_only_allocated(ptable_entity_t* entity, ptable_lv_t lv);
#endif // _KERNEL_PLATFORM_ARM32_VMM_MMU_H

26
kernel/include/platform/arm32/vmm/pde.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_VMM_PDE_H
#define _KERNEL_PLATFORM_ARM32_VMM_PDE_H
#include <libkern/c_attrs.h>
#include <libkern/types.h>
struct PACKED table_desc {
union {
struct {
int valid : 1; /* Valid mapping */
int zero1 : 1;
int zero2 : 1;
int ns : 1;
int zero3 : 1;
int domain : 4;
int imp : 1;
int baddr : 22;
};
uint32_t data;
};
};
typedef struct table_desc table_desc_t;
#define TABLE_DESC_FRAME_OFFSET 10
#endif //_KERNEL_PLATFORM_ARM32_VMM_PDE_H

31
kernel/include/platform/arm32/vmm/pte.h Normal file
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#ifndef _KERNEL_PLATFORM_ARM32_VMM_PTE_H
#define _KERNEL_PLATFORM_ARM32_VMM_PTE_H
#include <libkern/c_attrs.h>
#include <libkern/types.h>
#include <mem/bits/mmu.h>
typedef uint32_t ptable_entity_t;
struct PACKED page_desc {
union {
struct {
unsigned int xn : 1; // Execute never. Stops execution of page.
unsigned int one : 1; // Always one for tables
unsigned int b : 1; // cacheable
unsigned int c : 1; // Cacheable
unsigned int ap1 : 2;
unsigned int tex : 3;
unsigned int ap2 : 1;
unsigned int s : 1;
unsigned int ng : 1;
unsigned int baddr : 20;
};
uint32_t data;
};
};
typedef struct page_desc page_desc_t;
#define PAGE_DESC_FRAME_OFFSET 12
#endif //_KERNEL_PLATFORM_ARM32_VMM_PTE_H