/*
 * ---------------------------------------------------
 * Registers and Offsets of the Xilinx GPIO Peripheral
 * ---------------------------------------------------
 */

#define XGPIO_CHANNEL_1_OFFSET  0x0 // GPIO Channel 1 Base Offset.
#define XGPIO_CHANNEL_2_OFFSET  0x8 // GPIO Channel 2 Base Offset.

/*
 * GPIO Channel 1 Data Register.
 *
 * The Data Register of GPIO Channel 2 is XGPIO_DATA_OFFSET + XGPIO_CHANNEL_2_OFFSET.
 */
#define XGPIO_DATA_OFFSET  0x0

