
################################################################
# This is a generated script based on design: pcie_acceleration_vc707_design
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.4
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source pcie_acceleration_vc707_design_script.tcl

# If you do not already have a project created,
# you can create a project using the following command:
#    create_project project_1 myproj -part xc7vx485tffg1761-2
#    set_property BOARD_PART xilinx.com:vc707:part0:1.2 [current_project]

# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
   puts "ERROR: Please open or create a project!"
   return 1
}



# CHANGE DESIGN NAME HERE
set design_name pcie_acceleration_vc707_design

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "ERROR: Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      puts "INFO: Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   puts "INFO: Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   puts "INFO: Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   puts "INFO: Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

puts "INFO: Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   puts $errMsg
   return $nRet
}


##################################################################
# MIG PRJ FILE TCL PROCs
##################################################################

proc write_mig_file_pcie_acceleration_vc707_design_mig_7series_0_0 { str_mig_prj_filepath } {

   set mig_prj_file [open $str_mig_prj_filepath  w+]

   puts $mig_prj_file {<?xml version='1.0' encoding='UTF-8'?>}
   puts $mig_prj_file {<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->}
   puts $mig_prj_file {<Project NoOfControllers="1" >}
   puts $mig_prj_file {    <ModuleName>pcie_acceleration_vc707_design_mig_7series_0_0</ModuleName>}
   puts $mig_prj_file {    <dci_inouts_inputs>1</dci_inouts_inputs>}
   puts $mig_prj_file {    <dci_inputs>1</dci_inputs>}
   puts $mig_prj_file {    <Debug_En>OFF</Debug_En>}
   puts $mig_prj_file {    <DataDepth_En>1024</DataDepth_En>}
   puts $mig_prj_file {    <LowPower_En>ON</LowPower_En>}
   puts $mig_prj_file {    <XADC_En>Enabled</XADC_En>}
   puts $mig_prj_file {    <TargetFPGA>xc7vx485t-ffg1761/-2</TargetFPGA>}
   puts $mig_prj_file {    <Version>2.4</Version>}
   puts $mig_prj_file {    <SystemClock>No Buffer</SystemClock>}
   puts $mig_prj_file {    <ReferenceClock>Use System Clock</ReferenceClock>}
   puts $mig_prj_file {    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>}
   puts $mig_prj_file {    <BankSelectionFlag>FALSE</BankSelectionFlag>}
   puts $mig_prj_file {    <InternalVref>1</InternalVref>}
   puts $mig_prj_file {    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>}
   puts $mig_prj_file {    <dci_cascade>0</dci_cascade>}
   puts $mig_prj_file {    <Controller number="0" >}
   puts $mig_prj_file {        <MemoryDevice>DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6</MemoryDevice>}
   puts $mig_prj_file {        <TimePeriod>2500</TimePeriod>}
   puts $mig_prj_file {        <VccAuxIO>1.8V</VccAuxIO>}
   puts $mig_prj_file {        <PHYRatio>4:1</PHYRatio>}
   puts $mig_prj_file {        <InputClkFreq>200</InputClkFreq>}
   puts $mig_prj_file {        <UIExtraClocks>0</UIExtraClocks>}
   puts $mig_prj_file {        <MMCM_VCO>800</MMCM_VCO>}
   puts $mig_prj_file {        <MMCMClkOut0> 1.000</MMCMClkOut0>}
   puts $mig_prj_file {        <MMCMClkOut1>1</MMCMClkOut1>}
   puts $mig_prj_file {        <MMCMClkOut2>1</MMCMClkOut2>}
   puts $mig_prj_file {        <MMCMClkOut3>1</MMCMClkOut3>}
   puts $mig_prj_file {        <MMCMClkOut4>1</MMCMClkOut4>}
   puts $mig_prj_file {        <DataWidth>64</DataWidth>}
   puts $mig_prj_file {        <DeepMemory>1</DeepMemory>}
   puts $mig_prj_file {        <DataMask>1</DataMask>}
   puts $mig_prj_file {        <ECC>Disabled</ECC>}
   puts $mig_prj_file {        <Ordering>Normal</Ordering>}
   puts $mig_prj_file {        <CustomPart>FALSE</CustomPart>}
   puts $mig_prj_file {        <NewPartName></NewPartName>}
   puts $mig_prj_file {        <RowAddress>14</RowAddress>}
   puts $mig_prj_file {        <ColAddress>10</ColAddress>}
   puts $mig_prj_file {        <BankAddress>3</BankAddress>}
   puts $mig_prj_file {        <MemoryVoltage>1.5V</MemoryVoltage>}
   puts $mig_prj_file {        <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>}
   puts $mig_prj_file {        <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>}
   puts $mig_prj_file {        <PinSelection>}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A20" SLEW="" name="ddr3_addr[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_addr[10]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_addr[11]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A15" SLEW="" name="ddr3_addr[12]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A21" SLEW="" name="ddr3_addr[13]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_addr[1]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C20" SLEW="" name="ddr3_addr[2]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A19" SLEW="" name="ddr3_addr[3]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A16" SLEW="" name="ddr3_addr[5]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_addr[6]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C18" SLEW="" name="ddr3_addr[7]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D17" SLEW="" name="ddr3_addr[8]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D21" SLEW="" name="ddr3_ba[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_ba[1]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D18" SLEW="" name="ddr3_ba[2]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K17" SLEW="" name="ddr3_cas_n" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="G18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15" PADName="H19" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K19" SLEW="" name="ddr3_cke[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="J17" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="M13" SLEW="" name="ddr3_dm[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="K15" SLEW="" name="ddr3_dm[1]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F12" SLEW="" name="ddr3_dm[2]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="A14" SLEW="" name="ddr3_dm[3]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dm[4]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="D25" SLEW="" name="ddr3_dm[5]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="C31" SLEW="" name="ddr3_dm[6]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F31" SLEW="" name="ddr3_dm[7]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N14" SLEW="" name="ddr3_dq[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H13" SLEW="" name="ddr3_dq[10]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J13" SLEW="" name="ddr3_dq[11]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L16" SLEW="" name="ddr3_dq[12]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L15" SLEW="" name="ddr3_dq[13]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="H14" SLEW="" name="ddr3_dq[14]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="J15" SLEW="" name="ddr3_dq[15]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E15" SLEW="" name="ddr3_dq[16]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E13" SLEW="" name="ddr3_dq[17]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F15" SLEW="" name="ddr3_dq[18]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E14" SLEW="" name="ddr3_dq[19]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N13" SLEW="" name="ddr3_dq[1]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G13" SLEW="" name="ddr3_dq[20]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G12" SLEW="" name="ddr3_dq[21]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F14" SLEW="" name="ddr3_dq[22]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="G14" SLEW="" name="ddr3_dq[23]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B14" SLEW="" name="ddr3_dq[24]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C13" SLEW="" name="ddr3_dq[25]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B16" SLEW="" name="ddr3_dq[26]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D15" SLEW="" name="ddr3_dq[27]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D13" SLEW="" name="ddr3_dq[28]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E12" SLEW="" name="ddr3_dq[29]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L14" SLEW="" name="ddr3_dq[2]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C16" SLEW="" name="ddr3_dq[30]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D16" SLEW="" name="ddr3_dq[31]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A24" SLEW="" name="ddr3_dq[32]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B23" SLEW="" name="ddr3_dq[33]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B27" SLEW="" name="ddr3_dq[34]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B26" SLEW="" name="ddr3_dq[35]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A22" SLEW="" name="ddr3_dq[36]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B22" SLEW="" name="ddr3_dq[37]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A25" SLEW="" name="ddr3_dq[38]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C24" SLEW="" name="ddr3_dq[39]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M14" SLEW="" name="ddr3_dq[3]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E24" SLEW="" name="ddr3_dq[40]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D23" SLEW="" name="ddr3_dq[41]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D26" SLEW="" name="ddr3_dq[42]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C25" SLEW="" name="ddr3_dq[43]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E23" SLEW="" name="ddr3_dq[44]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D22" SLEW="" name="ddr3_dq[45]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F22" SLEW="" name="ddr3_dq[46]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E22" SLEW="" name="ddr3_dq[47]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A30" SLEW="" name="ddr3_dq[48]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D27" SLEW="" name="ddr3_dq[49]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M12" SLEW="" name="ddr3_dq[4]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A29" SLEW="" name="ddr3_dq[50]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C28" SLEW="" name="ddr3_dq[51]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D28" SLEW="" name="ddr3_dq[52]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="B31" SLEW="" name="ddr3_dq[53]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A31" SLEW="" name="ddr3_dq[54]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="A32" SLEW="" name="ddr3_dq[55]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E30" SLEW="" name="ddr3_dq[56]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F29" SLEW="" name="ddr3_dq[57]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F30" SLEW="" name="ddr3_dq[58]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F27" SLEW="" name="ddr3_dq[59]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="N15" SLEW="" name="ddr3_dq[5]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="C30" SLEW="" name="ddr3_dq[60]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="E29" SLEW="" name="ddr3_dq[61]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="F26" SLEW="" name="ddr3_dq[62]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="D30" SLEW="" name="ddr3_dq[63]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="M11" SLEW="" name="ddr3_dq[6]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="L12" SLEW="" name="ddr3_dq[7]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K14" SLEW="" name="ddr3_dq[8]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15_T_DCI" PADName="K13" SLEW="" name="ddr3_dq[9]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="M16" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="J12" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="G16" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C14" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A27" SLEW="" name="ddr3_dqs_n[4]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E25" SLEW="" name="ddr3_dqs_n[5]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B29" SLEW="" name="ddr3_dqs_n[6]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E28" SLEW="" name="ddr3_dqs_n[7]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="N16" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="K12" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="H16" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="C15" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="A26" SLEW="" name="ddr3_dqs_p[4]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="F25" SLEW="" name="ddr3_dqs_p[5]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="B28" SLEW="" name="ddr3_dqs_p[6]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="E27" SLEW="" name="ddr3_dqs_p[7]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="H20" SLEW="" name="ddr3_odt[0]" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_ras_n" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="LVCMOS15" PADName="C29" SLEW="" name="ddr3_reset_n" IN_TERM="" />}
   puts $mig_prj_file {            <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_we_n" IN_TERM="" />}
   puts $mig_prj_file {        </PinSelection>}
   puts $mig_prj_file {        <System_Control>}
   puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />}
   puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />}
   puts $mig_prj_file {            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />}
   puts $mig_prj_file {        </System_Control>}
   puts $mig_prj_file {        <TimingParameters>}
   puts $mig_prj_file {            <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />}
   puts $mig_prj_file {        </TimingParameters>}
   puts $mig_prj_file {        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>}
   puts $mig_prj_file {        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>}
   puts $mig_prj_file {        <mrCasLatency name="CAS Latency" >6</mrCasLatency>}
   puts $mig_prj_file {        <mrMode name="Mode" >Normal</mrMode>}
   puts $mig_prj_file {        <mrDllReset name="DLL Reset" >No</mrDllReset>}
   puts $mig_prj_file {        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>}
   puts $mig_prj_file {        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>}
   puts $mig_prj_file {        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>}
   puts $mig_prj_file {        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>}
   puts $mig_prj_file {        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>}
   puts $mig_prj_file {        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>}
   puts $mig_prj_file {        <emrPosted name="Additive Latency (AL)" >0</emrPosted>}
   puts $mig_prj_file {        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>}
   puts $mig_prj_file {        <emrDQS name="TDQS enable" >Enabled</emrDQS>}
   puts $mig_prj_file {        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>}
   puts $mig_prj_file {        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>}
   puts $mig_prj_file {        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>}
   puts $mig_prj_file {        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>}
   puts $mig_prj_file {        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>}
   puts $mig_prj_file {        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>}
   puts $mig_prj_file {        <PortInterface>AXI</PortInterface>}
   puts $mig_prj_file {        <AXIParameters>}
   puts $mig_prj_file {            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>}
   puts $mig_prj_file {            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>}
   puts $mig_prj_file {            <C0_S_AXI_DATA_WIDTH>128</C0_S_AXI_DATA_WIDTH>}
   puts $mig_prj_file {            <C0_S_AXI_ID_WIDTH>6</C0_S_AXI_ID_WIDTH>}
   puts $mig_prj_file {            <C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>}
   puts $mig_prj_file {        </AXIParameters>}
   puts $mig_prj_file {    </Controller>}
   puts $mig_prj_file {</Project>}

   close $mig_prj_file
}
# End of write_mig_file_pcie_acceleration_vc707_design_mig_7series_0_0()



##################################################################
# DESIGN PROCs
##################################################################


# Hierarchical cell: microblaze_bram
proc create_hier_cell_microblaze_bram { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_microblaze_bram() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB

  # Create pins
  create_bd_pin -dir I -type clk LMB_Clk
  create_bd_pin -dir I -from 0 -to 0 -type rst SYS_Rst

  # Create instance: dlmb_bram_if_cntlr, and set properties
  set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
  set_property -dict [ list \
CONFIG.C_ECC {0} \
 ] $dlmb_bram_if_cntlr

  # Create instance: dlmb_v10, and set properties
  set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]

  # Create instance: ilmb_bram_if_cntlr, and set properties
  set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
  set_property -dict [ list \
CONFIG.C_ECC {0} \
 ] $ilmb_bram_if_cntlr

  # Create instance: ilmb_v10, and set properties
  set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]

  # Create instance: lmb_bram, and set properties
  set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 lmb_bram ]
  set_property -dict [ list \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.use_bram_block {BRAM_Controller} \
 ] $lmb_bram

  # Create interface connections
  connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
  connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
  connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
  connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
  connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
  connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]

  # Create port connections
  connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_sg
proc create_hier_cell_accel_group_sg { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_sg() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_cfg_V
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -type intr interrupt
  create_bd_pin -dir O -type intr interrupt1
  create_bd_pin -dir O -type intr s2mm_introut

  # Create instance: acceleration_scheduler_sg_xdma, and set properties
  set acceleration_scheduler_sg_xdma [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_sg_xdma:3.5 acceleration_scheduler_sg_xdma ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: dma_sg_pcie_scheduler, and set properties
  set dma_sg_pcie_scheduler [ create_bd_cell -type ip -vlnv xilinx.com:hls:dma_sg_pcie_scheduler:1.0 dma_sg_pcie_scheduler ]

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {5} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_sg_xdma/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axi_cfg_V] [get_bd_intf_pins dma_sg_pcie_scheduler/m_axi_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins dma_sg_pcie_scheduler/s_axi_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_M04_AXI [get_bd_intf_pins acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg] [get_bd_intf_pins ic_accel/M04_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_sg_xdma_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_sg_xdma/interrupt]
  connect_bd_net -net dma_mm2s_introut [get_bd_pins dma/mm2s_introut] [get_bd_pins dma_sg_pcie_scheduler/mm2s_intr_in_V]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins dma/s2mm_introut] [get_bd_pins dma_sg_pcie_scheduler/s2mm_intr_in_V]
  connect_bd_net -net dma_sg_pcie_scheduler_interrupt [get_bd_pins interrupt1] [get_bd_pins acceleration_scheduler_sg_xdma/scheduler_intr_in_V] [get_bd_pins dma_sg_pcie_scheduler/interrupt]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_sg_xdma/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins dma_sg_pcie_scheduler/ap_clk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/M04_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_sg_xdma/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins dma_sg_pcie_scheduler/ap_rst_n] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/M04_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_indirect_3
proc create_hier_cell_accel_group_indirect_3 { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_indirect_3() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -type intr interrupt
  create_bd_pin -dir O -type intr s2mm_introut
  create_bd_pin -dir I -from 0 -to 0 -type data start_V

  # Create instance: acceleration_scheduler_indirect, and set properties
  set acceleration_scheduler_indirect [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_indirect:2.0 acceleration_scheduler_indirect ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {4} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_indirect/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins acceleration_scheduler_indirect/s_axi_int_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_indirect_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_indirect/interrupt]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins acceleration_scheduler_indirect/dma_intr_in_V] [get_bd_pins dma/s2mm_introut]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_indirect/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_indirect/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]
  connect_bd_net -net start_V_1 [get_bd_pins start_V] [get_bd_pins acceleration_scheduler_indirect/start_V]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_indirect_2
proc create_hier_cell_accel_group_indirect_2 { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_indirect_2() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -type intr interrupt
  create_bd_pin -dir O -type intr s2mm_introut
  create_bd_pin -dir I -from 0 -to 0 -type data start_V

  # Create instance: acceleration_scheduler_indirect, and set properties
  set acceleration_scheduler_indirect [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_indirect:2.0 acceleration_scheduler_indirect ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {4} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_indirect/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins acceleration_scheduler_indirect/s_axi_int_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_indirect_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_indirect/interrupt]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins acceleration_scheduler_indirect/dma_intr_in_V] [get_bd_pins dma/s2mm_introut]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_indirect/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_indirect/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]
  connect_bd_net -net start_V_1 [get_bd_pins start_V] [get_bd_pins acceleration_scheduler_indirect/start_V]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_indirect_1
proc create_hier_cell_accel_group_indirect_1 { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_indirect_1() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -type intr interrupt
  create_bd_pin -dir O -type intr s2mm_introut
  create_bd_pin -dir I -from 0 -to 0 -type data start_V

  # Create instance: acceleration_scheduler_indirect, and set properties
  set acceleration_scheduler_indirect [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_indirect:2.0 acceleration_scheduler_indirect ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {4} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_indirect/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins acceleration_scheduler_indirect/s_axi_int_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_indirect_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_indirect/interrupt]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins acceleration_scheduler_indirect/dma_intr_in_V] [get_bd_pins dma/s2mm_introut]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_indirect/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_indirect/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]
  connect_bd_net -net start_V_1 [get_bd_pins start_V] [get_bd_pins acceleration_scheduler_indirect/start_V]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_indirect_0
proc create_hier_cell_accel_group_indirect_0 { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_indirect_0() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -type intr interrupt
  create_bd_pin -dir O -type intr s2mm_introut
  create_bd_pin -dir I -from 0 -to 0 -type data start_V

  # Create instance: acceleration_scheduler_indirect, and set properties
  set acceleration_scheduler_indirect [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_indirect:2.0 acceleration_scheduler_indirect ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {4} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_indirect/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins acceleration_scheduler_indirect/s_axi_int_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_indirect_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_indirect/interrupt]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins s2mm_introut] [get_bd_pins acceleration_scheduler_indirect/dma_intr_in_V] [get_bd_pins dma/s2mm_introut]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_indirect/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_indirect/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]
  connect_bd_net -net start_V_1 [get_bd_pins start_V] [get_bd_pins acceleration_scheduler_indirect/start_V]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_direct_1
proc create_hier_cell_accel_group_direct_1 { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_direct_1() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mm2s_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -from 0 -to 0 -type data dma_intr_in_V
  create_bd_pin -dir O -type intr interrupt

  # Create instance: acceleration_scheduler_direct, and set properties
  set acceleration_scheduler_direct [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_direct:3.5 acceleration_scheduler_direct ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {4} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_mm2s_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_direct/m_axi_mm2s_ext_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins acceleration_scheduler_direct/s_axi_mm2s_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_direct_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_direct/interrupt]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins dma_intr_in_V] [get_bd_pins acceleration_scheduler_direct/dma_intr_in_V] [get_bd_pins dma/s2mm_introut]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_direct/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_direct/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]

  # Restore current instance
  current_bd_instance $oldCurInst
}

# Hierarchical cell: accel_group_direct_0
proc create_hier_cell_accel_group_direct_0 { parentCell nameHier } {

  if { $parentCell eq "" || $nameHier eq "" } {
     puts "ERROR: create_hier_cell_accel_group_direct_0() - Empty argument(s)!"
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_MM2S
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI_S2MM
  create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 m_axi_mm2s_ext_cfg_V

  # Create pins
  create_bd_pin -dir I -type clk ACLK
  create_bd_pin -dir I -from 0 -to 0 -type rst ARESETN
  create_bd_pin -dir I -from 0 -to 0 -type rst S00_ARESETN
  create_bd_pin -dir O -from 0 -to 0 -type data dma_intr_in_V
  create_bd_pin -dir O -type intr interrupt

  # Create instance: acceleration_scheduler_direct, and set properties
  set acceleration_scheduler_direct [ create_bd_cell -type ip -vlnv xilinx.com:hls:acceleration_scheduler_direct:3.5 acceleration_scheduler_direct ]

  # Create instance: apm, and set properties
  set apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 apm ]
  set_property -dict [ list \
CONFIG.C_NUM_MONITOR_SLOTS {3} \
CONFIG.C_NUM_OF_COUNTERS {6} \
CONFIG.C_SLOT_2_AXI_PROTOCOL {AXI4S} \
 ] $apm

  # Create instance: dma, and set properties
  set dma [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 dma ]
  set_property -dict [ list \
CONFIG.c_include_mm2s_dre {1} \
CONFIG.c_include_s2mm_dre {1} \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {128} \
CONFIG.c_m_axi_s2mm_data_width {128} \
CONFIG.c_mm2s_burst_size {32} \
CONFIG.c_s2mm_burst_size {32} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {23} \
 ] $dma

  # Create instance: ic_accel, and set properties
  set ic_accel [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.NUM_MI {4} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel

  # Create instance: sobel_filter, and set properties
  set sobel_filter [ create_bd_cell -type ip -vlnv xilinx.com:hls:sobel_filter:5.8 sobel_filter ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axi_mm2s_ext_cfg_V] [get_bd_intf_pins acceleration_scheduler_direct/m_axi_mm2s_ext_cfg_V]
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins dma/M_AXI_MM2S]
  connect_bd_intf_net -intf_net [get_bd_intf_nets S00_AXI_1] [get_bd_intf_pins M_AXI_MM2S] [get_bd_intf_pins apm/SLOT_0_AXI]
  connect_bd_intf_net -intf_net dma_M_AXIS_MM2S [get_bd_intf_pins dma/M_AXIS_MM2S] [get_bd_intf_pins sobel_filter/STREAM_IN]
  connect_bd_intf_net -intf_net dma_M_AXI_S2MM [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins dma/M_AXI_S2MM]
  connect_bd_intf_net -intf_net [get_bd_intf_nets dma_M_AXI_S2MM] [get_bd_intf_pins M_AXI_S2MM] [get_bd_intf_pins apm/SLOT_1_AXI]
  connect_bd_intf_net -intf_net ic_accel_M00_AXI [get_bd_intf_pins acceleration_scheduler_direct/s_axi_mm2s_cfg] [get_bd_intf_pins ic_accel/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_M01_AXI [get_bd_intf_pins dma/S_AXI_LITE] [get_bd_intf_pins ic_accel/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_M02_AXI [get_bd_intf_pins ic_accel/M02_AXI] [get_bd_intf_pins sobel_filter/s_axi_S_AXI4_LITE]
  connect_bd_intf_net -intf_net ic_accel_M03_AXI [get_bd_intf_pins apm/S_AXI] [get_bd_intf_pins ic_accel/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins S00_AXI] [get_bd_intf_pins ic_accel/S00_AXI]
  connect_bd_intf_net -intf_net sobel_filter_STREAM_OUT [get_bd_intf_pins dma/S_AXIS_S2MM] [get_bd_intf_pins sobel_filter/STREAM_OUT]
  connect_bd_intf_net -intf_net [get_bd_intf_nets sobel_filter_STREAM_OUT] [get_bd_intf_pins apm/SLOT_2_AXIS] [get_bd_intf_pins sobel_filter/STREAM_OUT]

  # Create port connections
  connect_bd_net -net acceleration_scheduler_direct_interrupt [get_bd_pins interrupt] [get_bd_pins acceleration_scheduler_direct/interrupt]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins dma_intr_in_V] [get_bd_pins acceleration_scheduler_direct/dma_intr_in_V] [get_bd_pins dma/s2mm_introut]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins ACLK] [get_bd_pins acceleration_scheduler_direct/ap_clk] [get_bd_pins apm/core_aclk] [get_bd_pins apm/s_axi_aclk] [get_bd_pins apm/slot_0_axi_aclk] [get_bd_pins apm/slot_1_axi_aclk] [get_bd_pins apm/slot_2_axis_aclk] [get_bd_pins dma/m_axi_mm2s_aclk] [get_bd_pins dma/m_axi_s2mm_aclk] [get_bd_pins dma/s_axi_lite_aclk] [get_bd_pins ic_accel/ACLK] [get_bd_pins ic_accel/M00_ACLK] [get_bd_pins ic_accel/M01_ACLK] [get_bd_pins ic_accel/M02_ACLK] [get_bd_pins ic_accel/M03_ACLK] [get_bd_pins ic_accel/S00_ACLK] [get_bd_pins sobel_filter/ap_clk]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins ARESETN] [get_bd_pins ic_accel/ARESETN]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins S00_ARESETN] [get_bd_pins acceleration_scheduler_direct/ap_rst_n] [get_bd_pins apm/core_aresetn] [get_bd_pins apm/s_axi_aresetn] [get_bd_pins apm/slot_0_axi_aresetn] [get_bd_pins apm/slot_1_axi_aresetn] [get_bd_pins apm/slot_2_axis_aresetn] [get_bd_pins dma/axi_resetn] [get_bd_pins ic_accel/M00_ARESETN] [get_bd_pins ic_accel/M01_ARESETN] [get_bd_pins ic_accel/M02_ARESETN] [get_bd_pins ic_accel/M03_ARESETN] [get_bd_pins ic_accel/S00_ARESETN] [get_bd_pins sobel_filter/ap_rst_n]

  # Restore current instance
  current_bd_instance $oldCurInst
}


# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     puts "ERROR: Unable to find parent cell <$parentCell>!"
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set ddr3_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3_sdram ]
  set pcie_7x_mgt [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:pcie_7x_mgt_rtl:1.0 pcie_7x_mgt ]
  set rs232_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart ]
  set sys_diff_clock [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]
  set_property -dict [ list \
CONFIG.FREQ_HZ {200000000} \
 ] $sys_diff_clock

  # Create ports
  set REFCLK [ create_bd_port -dir I -type clk REFCLK ]
  set init_calib_complete [ create_bd_port -dir O init_calib_complete ]
  set perst [ create_bd_port -dir I -type rst perst ]
  set reset [ create_bd_port -dir I -type rst reset ]
  set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_HIGH} \
 ] $reset

  # Create instance: accel_group_direct_0
  create_hier_cell_accel_group_direct_0 [current_bd_instance .] accel_group_direct_0

  # Create instance: accel_group_direct_1
  create_hier_cell_accel_group_direct_1 [current_bd_instance .] accel_group_direct_1

  # Create instance: accel_group_indirect_0
  create_hier_cell_accel_group_indirect_0 [current_bd_instance .] accel_group_indirect_0

  # Create instance: accel_group_indirect_1
  create_hier_cell_accel_group_indirect_1 [current_bd_instance .] accel_group_indirect_1

  # Create instance: accel_group_indirect_2
  create_hier_cell_accel_group_indirect_2 [current_bd_instance .] accel_group_indirect_2

  # Create instance: accel_group_indirect_3
  create_hier_cell_accel_group_indirect_3 [current_bd_instance .] accel_group_indirect_3

  # Create instance: accel_group_sg
  create_hier_cell_accel_group_sg [current_bd_instance .] accel_group_sg

  # Create instance: axi_interrupt_controller, and set properties
  set axi_interrupt_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_interrupt_controller ]
  set_property -dict [ list \
CONFIG.C_HAS_FAST {1} \
 ] $axi_interrupt_controller

  # Create instance: axi_uartlite, and set properties
  set axi_uartlite [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite ]
  set_property -dict [ list \
CONFIG.UARTLITE_BOARD_INTERFACE {rs232_uart} \
CONFIG.USE_BOARD_FLOW {true} \
 ] $axi_uartlite

  # Create instance: cdma_fetch, and set properties
  set cdma_fetch [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_cdma:4.1 cdma_fetch ]
  set_property -dict [ list \
CONFIG.C_INCLUDE_DRE {1} \
CONFIG.C_INCLUDE_SG {0} \
CONFIG.C_M_AXI_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MAX_BURST_LEN {64} \
 ] $cdma_fetch

  # Create instance: cdma_send, and set properties
  set cdma_send [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_cdma:4.1 cdma_send ]
  set_property -dict [ list \
CONFIG.C_INCLUDE_DRE {1} \
CONFIG.C_INCLUDE_SG {0} \
CONFIG.C_M_AXI_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MAX_BURST_LEN {64} \
 ] $cdma_send

  # Create instance: clocking_wizard, and set properties
  set clocking_wizard [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.2 clocking_wizard ]
  set_property -dict [ list \
CONFIG.CLKOUT1_JITTER {107.523} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000} \
CONFIG.CLKOUT2_JITTER {98.146} \
CONFIG.CLKOUT2_PHASE_ERROR {89.971} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200.000} \
CONFIG.CLKOUT2_USED {true} \
CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {5} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.NUM_OUT_CLKS {2} \
CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
CONFIG.USE_BOARD_FLOW {true} \
 ] $clocking_wizard

  # Create instance: fetch_scheduler, and set properties
  set fetch_scheduler [ create_bd_cell -type ip -vlnv xilinx.com:hls:fetch_scheduler:1.0 fetch_scheduler ]

  # Create instance: gpio_ack, and set properties
  set gpio_ack [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_ack ]
  set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_GPIO_WIDTH {1} \
 ] $gpio_ack

  # Create instance: gpio_msi, and set properties
  set gpio_msi [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_msi ]
  set_property -dict [ list \
CONFIG.C_ALL_INPUTS_2 {0} \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {5} \
CONFIG.C_GPIO_WIDTH {1} \
CONFIG.C_IS_DUAL {1} \
 ] $gpio_msi

  # Create instance: gpio_msi_read, and set properties
  set gpio_msi_read [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_msi_read ]
  set_property -dict [ list \
CONFIG.C_ALL_INPUTS {1} \
CONFIG.C_GPIO_WIDTH {5} \
 ] $gpio_msi_read

  # Create instance: gpio_pcie_interrupt, and set properties
  set gpio_pcie_interrupt [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 gpio_pcie_interrupt ]
  set_property -dict [ list \
CONFIG.C_ALL_INPUTS_2 {1} \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_INTERRUPT_PRESENT {1} \
CONFIG.C_IS_DUAL {1} \
 ] $gpio_pcie_interrupt

  # Create instance: ic_accel_groups, and set properties
  set ic_accel_groups [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_accel_groups ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.M04_HAS_REGSLICE {3} \
CONFIG.M05_HAS_REGSLICE {3} \
CONFIG.M06_HAS_REGSLICE {3} \
CONFIG.M07_HAS_REGSLICE {3} \
CONFIG.M08_HAS_REGSLICE {3} \
CONFIG.NUM_MI {9} \
CONFIG.S00_HAS_REGSLICE {3} \
 ] $ic_accel_groups

  # Create instance: ic_dmas, and set properties
  set ic_dmas [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_dmas ]
  set_property -dict [ list \
CONFIG.M00_HAS_DATA_FIFO {2} \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {14} \
CONFIG.S00_HAS_DATA_FIFO {2} \
CONFIG.S00_HAS_REGSLICE {3} \
CONFIG.S01_HAS_DATA_FIFO {2} \
CONFIG.S01_HAS_REGSLICE {3} \
CONFIG.S02_HAS_DATA_FIFO {2} \
CONFIG.S02_HAS_REGSLICE {3} \
CONFIG.S03_HAS_DATA_FIFO {2} \
CONFIG.S03_HAS_REGSLICE {3} \
CONFIG.S04_HAS_DATA_FIFO {2} \
CONFIG.S04_HAS_REGSLICE {3} \
CONFIG.S05_HAS_DATA_FIFO {2} \
CONFIG.S05_HAS_REGSLICE {3} \
CONFIG.S06_HAS_DATA_FIFO {2} \
CONFIG.S06_HAS_REGSLICE {3} \
CONFIG.S07_HAS_DATA_FIFO {2} \
CONFIG.S07_HAS_REGSLICE {3} \
CONFIG.S08_HAS_DATA_FIFO {2} \
CONFIG.S08_HAS_REGSLICE {3} \
CONFIG.S09_HAS_DATA_FIFO {2} \
CONFIG.S09_HAS_REGSLICE {3} \
CONFIG.S10_HAS_DATA_FIFO {2} \
CONFIG.S10_HAS_REGSLICE {3} \
CONFIG.S11_HAS_DATA_FIFO {2} \
CONFIG.S11_HAS_REGSLICE {3} \
CONFIG.S12_HAS_DATA_FIFO {2} \
CONFIG.S12_HAS_REGSLICE {3} \
CONFIG.S13_HAS_DATA_FIFO {2} \
CONFIG.S13_HAS_REGSLICE {3} \
CONFIG.STRATEGY {2} \
 ] $ic_dmas

  # Create instance: ic_main, and set properties
  set ic_main [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_main ]
  set_property -dict [ list \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.M02_HAS_REGSLICE {3} \
CONFIG.M03_HAS_REGSLICE {3} \
CONFIG.M04_HAS_REGSLICE {3} \
CONFIG.M05_HAS_REGSLICE {3} \
CONFIG.M06_HAS_REGSLICE {3} \
CONFIG.M07_HAS_REGSLICE {3} \
CONFIG.M08_HAS_REGSLICE {3} \
CONFIG.M09_HAS_REGSLICE {3} \
CONFIG.M10_HAS_REGSLICE {3} \
CONFIG.M11_HAS_REGSLICE {3} \
CONFIG.M12_HAS_REGSLICE {3} \
CONFIG.M13_HAS_REGSLICE {3} \
CONFIG.M14_HAS_REGSLICE {3} \
CONFIG.M15_HAS_REGSLICE {3} \
CONFIG.NUM_MI {16} \
CONFIG.NUM_SI {13} \
CONFIG.S00_HAS_REGSLICE {3} \
CONFIG.S01_HAS_REGSLICE {3} \
CONFIG.S02_HAS_REGSLICE {3} \
CONFIG.S03_HAS_REGSLICE {3} \
CONFIG.S04_HAS_REGSLICE {3} \
CONFIG.S05_HAS_REGSLICE {3} \
CONFIG.S06_HAS_REGSLICE {3} \
CONFIG.S07_HAS_REGSLICE {3} \
CONFIG.S08_HAS_REGSLICE {3} \
CONFIG.S09_HAS_REGSLICE {3} \
CONFIG.S10_HAS_REGSLICE {3} \
CONFIG.S11_HAS_REGSLICE {3} \
CONFIG.S12_HAS_REGSLICE {3} \
 ] $ic_main

  # Create instance: ic_pcie_mig, and set properties
  set ic_pcie_mig [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ic_pcie_mig ]
  set_property -dict [ list \
CONFIG.M00_HAS_DATA_FIFO {2} \
CONFIG.M00_HAS_REGSLICE {3} \
CONFIG.M01_HAS_DATA_FIFO {2} \
CONFIG.M01_HAS_REGSLICE {3} \
CONFIG.NUM_MI {2} \
CONFIG.NUM_SI {4} \
CONFIG.S00_HAS_DATA_FIFO {2} \
CONFIG.S00_HAS_REGSLICE {3} \
CONFIG.S01_HAS_DATA_FIFO {2} \
CONFIG.S01_HAS_REGSLICE {3} \
CONFIG.S02_HAS_DATA_FIFO {2} \
CONFIG.S02_HAS_REGSLICE {3} \
CONFIG.S03_HAS_DATA_FIFO {2} \
CONFIG.S03_HAS_REGSLICE {3} \
CONFIG.STRATEGY {2} \
 ] $ic_pcie_mig

  # Create instance: interrupt_manager, and set properties
  set interrupt_manager [ create_bd_cell -type ip -vlnv xilinx.com:hls:interrupt_manager:3.5 interrupt_manager ]

  # Create instance: mdm, and set properties
  set mdm [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm ]

  # Create instance: microblaze_0, and set properties
  set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.5 microblaze_0 ]
  set_property -dict [ list \
CONFIG.C_DEBUG_ENABLED {1} \
CONFIG.C_D_AXI {1} \
CONFIG.C_D_LMB {1} \
CONFIG.C_I_LMB {1} \
 ] $microblaze_0

  # Create instance: microblaze_bram
  create_hier_cell_microblaze_bram [current_bd_instance .] microblaze_bram

  # Create instance: mig, and set properties
  set mig [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 mig ]

  # Generate the PRJ File for MIG
  set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig ] ] ]
  set str_mig_file_name mig_b.prj
  set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}

  write_mig_file_pcie_acceleration_vc707_design_mig_7series_0_0 $str_mig_file_path

  set_property -dict [ list \
CONFIG.BOARD_MIG_PARAM {ddr3_sdram} \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.XML_INPUT_FILE {mig_b.prj} \
 ] $mig

  # Create instance: pcie, and set properties
  set pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_pcie:2.7 pcie ]
  set_property -dict [ list \
CONFIG.AXIBAR2PCIEBAR_0 {0x00000000} \
CONFIG.AXIBAR_AS_0 {true} \
CONFIG.AXIBAR_AS_1 {true} \
CONFIG.AXIBAR_AS_2 {true} \
CONFIG.AXIBAR_AS_3 {true} \
CONFIG.AXIBAR_AS_4 {true} \
CONFIG.AXIBAR_AS_5 {true} \
CONFIG.AXIBAR_NUM {6} \
CONFIG.BAR0_SCALE {Megabytes} \
CONFIG.BAR0_SIZE {4} \
CONFIG.BAR1_ENABLED {true} \
CONFIG.BAR1_SCALE {Kilobytes} \
CONFIG.BAR1_SIZE {256} \
CONFIG.BAR1_TYPE {Memory} \
CONFIG.BAR2_ENABLED {true} \
CONFIG.BAR2_SCALE {Megabytes} \
CONFIG.BAR2_SIZE {512} \
CONFIG.BAR2_TYPE {Memory} \
CONFIG.BAR_64BIT {true} \
CONFIG.BASE_CLASS_MENU {Processors} \
CONFIG.CLASS_CODE {0x0B4000} \
CONFIG.COMP_TIMEOUT {50ms} \
CONFIG.DEVICE_ID {0x7022} \
CONFIG.ENABLE_CLASS_CODE {false} \
CONFIG.INTERRUPT_PIN {true} \
CONFIG.MAX_LINK_SPEED {5.0_GT/s} \
CONFIG.M_AXI_DATA_WIDTH {128} \
CONFIG.NO_OF_LANES {X4} \
CONFIG.NUM_MSI_REQ {5} \
CONFIG.PCIEBAR2AXIBAR_0 {0x10000000} \
CONFIG.PCIEBAR2AXIBAR_1 {0xC0000000} \
CONFIG.PCIEBAR2AXIBAR_2 {0x80000000} \
CONFIG.PCIE_USE_MODE {GES_and_Production} \
CONFIG.SUB_CLASS_INTERFACE_MENU {Co_processor} \
CONFIG.S_AXI_DATA_WIDTH {128} \
CONFIG.S_AXI_SUPPORTS_NARROW_BURST {true} \
CONFIG.XLNX_REF_BOARD {VC707} \
 ] $pcie

  # Create instance: psr_main, and set properties
  set psr_main [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_main ]
  set_property -dict [ list \
CONFIG.RESET_BOARD_INTERFACE {reset} \
CONFIG.USE_BOARD_FLOW {true} \
 ] $psr_main

  # Create instance: psr_mig, and set properties
  set psr_mig [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_mig ]

  # Create instance: psr_pcie, and set properties
  set psr_pcie [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 psr_pcie ]

  # Create instance: info_memory_block_fetch, and set properties
  set info_memory_block_fetch [ create_bd_cell -type ip -vlnv xilinx.com:hls:info_memory_block:1.0 info_memory_block_fetch ]

  # Create instance: info_memory_block_send, and set properties
  set info_memory_block_send [ create_bd_cell -type ip -vlnv xilinx.com:hls:info_memory_block:1.0 info_memory_block_send ]

  # Create instance: send_scheduler, and set properties
  set send_scheduler [ create_bd_cell -type ip -vlnv xilinx.com:hls:send_scheduler:3.0 send_scheduler ]

  # Create instance: shared_apm, and set properties
  set shared_apm [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_perf_mon:5.0 shared_apm ]
  set_property -dict [ list \
CONFIG.C_ENABLE_EVENT_COUNT {1} \
CONFIG.C_GLOBAL_COUNT_WIDTH {64} \
CONFIG.C_HAVE_SAMPLED_METRIC_CNT {0} \
 ] $shared_apm

  # Create instance: shared_metrics_bram_controller, and set properties
  set shared_metrics_bram_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.0 shared_metrics_bram_controller ]
  set_property -dict [ list \
CONFIG.SINGLE_PORT_BRAM {1} \
 ] $shared_metrics_bram_controller

  # Create instance: shared_metrics_bram_controller_bram, and set properties
  set shared_metrics_bram_controller_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 shared_metrics_bram_controller_bram ]

  # Create instance: xlconcat, and set properties
  set xlconcat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat ]
  set_property -dict [ list \
CONFIG.NUM_PORTS {20} \
 ] $xlconcat

  # Create interface connections
  connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins accel_group_direct_0/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S00_AXI]
  connect_bd_intf_net -intf_net S01_AXI_1 [get_bd_intf_pins ic_main/S01_AXI] [get_bd_intf_pins pcie/M_AXI]
  connect_bd_intf_net -intf_net S01_AXI_2 [get_bd_intf_pins accel_group_direct_0/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S01_AXI]
  connect_bd_intf_net -intf_net S01_AXI_3 [get_bd_intf_pins ic_dmas/M00_AXI] [get_bd_intf_pins ic_pcie_mig/S01_AXI]
  connect_bd_intf_net -intf_net S02_AXI_1 [get_bd_intf_pins accel_group_direct_0/m_axi_mm2s_ext_cfg_V] [get_bd_intf_pins ic_main/S02_AXI]
  connect_bd_intf_net -intf_net S02_AXI_2 [get_bd_intf_pins accel_group_direct_1/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S02_AXI]
  connect_bd_intf_net -intf_net S02_AXI_3 [get_bd_intf_pins cdma_fetch/M_AXI] [get_bd_intf_pins ic_pcie_mig/S02_AXI]
  connect_bd_intf_net -intf_net S03_AXI_1 [get_bd_intf_pins accel_group_direct_1/m_axi_mm2s_ext_cfg_V] [get_bd_intf_pins ic_main/S03_AXI]
  connect_bd_intf_net -intf_net S03_AXI_2 [get_bd_intf_pins cdma_send/M_AXI] [get_bd_intf_pins ic_pcie_mig/S03_AXI]
  connect_bd_intf_net -intf_net S04_AXI_1 [get_bd_intf_pins fetch_scheduler/m_axi_ext_cfg_V] [get_bd_intf_pins ic_main/S04_AXI]
  connect_bd_intf_net -intf_net S05_AXI_1 [get_bd_intf_pins ic_main/S05_AXI] [get_bd_intf_pins send_scheduler/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net S05_AXI_2 [get_bd_intf_pins accel_group_indirect_0/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S05_AXI]
  connect_bd_intf_net -intf_net S06_AXI_1 [get_bd_intf_pins accel_group_indirect_0/m_axi_ext_cfg_V] [get_bd_intf_pins ic_main/S06_AXI]
  connect_bd_intf_net -intf_net S06_AXI_2 [get_bd_intf_pins accel_group_indirect_1/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S06_AXI]
  connect_bd_intf_net -intf_net S09_AXI_1 [get_bd_intf_pins accel_group_indirect_2/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S09_AXI]
  connect_bd_intf_net -intf_net S10_AXI_1 [get_bd_intf_pins accel_group_sg/m_axi_ext_cfg_V] [get_bd_intf_pins ic_main/S10_AXI]
  connect_bd_intf_net -intf_net S11_AXI_1 [get_bd_intf_pins accel_group_indirect_3/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S11_AXI]
  connect_bd_intf_net -intf_net S11_AXI_2 [get_bd_intf_pins accel_group_sg/m_axi_cfg_V] [get_bd_intf_pins ic_main/S11_AXI]
  connect_bd_intf_net -intf_net S13_AXI_1 [get_bd_intf_pins accel_group_sg/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S13_AXI]
  connect_bd_intf_net -intf_net accel_group_direct_1_M_AXI_S2MM [get_bd_intf_pins accel_group_direct_1/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S03_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_0_M_AXI_MM2S [get_bd_intf_pins accel_group_indirect_0/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S04_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_1_M_AXI_S2MM [get_bd_intf_pins accel_group_indirect_1/M_AXI_S2MM] [get_bd_intf_pins ic_dmas/S07_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_1_m_axi_ext_cfg_V [get_bd_intf_pins accel_group_indirect_1/m_axi_ext_cfg_V] [get_bd_intf_pins ic_main/S07_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_2_M_AXI_MM2S [get_bd_intf_pins accel_group_indirect_2/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S08_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_2_m_axi_ext_cfg_V [get_bd_intf_pins accel_group_indirect_2/m_axi_ext_cfg_V] [get_bd_intf_pins ic_main/S08_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_3_M_AXI_MM2S [get_bd_intf_pins accel_group_indirect_3/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S10_AXI]
  connect_bd_intf_net -intf_net accel_group_indirect_3_m_axi_ext_cfg_V [get_bd_intf_pins accel_group_indirect_3/m_axi_ext_cfg_V] [get_bd_intf_pins ic_main/S09_AXI]
  connect_bd_intf_net -intf_net accel_group_sg_M_AXI_MM2S [get_bd_intf_pins accel_group_sg/M_AXI_MM2S] [get_bd_intf_pins ic_dmas/S12_AXI]
  connect_bd_intf_net -intf_net axi_uartlite_UART [get_bd_intf_ports rs232_uart] [get_bd_intf_pins axi_uartlite/UART]
  connect_bd_intf_net -intf_net ic_accel_groups_M00_AXI [get_bd_intf_pins accel_group_direct_0/S00_AXI] [get_bd_intf_pins ic_accel_groups/M00_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M01_AXI [get_bd_intf_pins accel_group_direct_1/S00_AXI] [get_bd_intf_pins ic_accel_groups/M01_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M02_AXI [get_bd_intf_pins accel_group_indirect_0/S00_AXI] [get_bd_intf_pins ic_accel_groups/M02_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M03_AXI [get_bd_intf_pins accel_group_indirect_1/S00_AXI] [get_bd_intf_pins ic_accel_groups/M03_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M04_AXI [get_bd_intf_pins accel_group_indirect_2/S00_AXI] [get_bd_intf_pins ic_accel_groups/M04_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M05_AXI [get_bd_intf_pins accel_group_indirect_3/S00_AXI] [get_bd_intf_pins ic_accel_groups/M05_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M06_AXI [get_bd_intf_pins accel_group_sg/S00_AXI] [get_bd_intf_pins ic_accel_groups/M06_AXI]
  connect_bd_intf_net -intf_net ic_accel_groups_M07_AXI [get_bd_intf_pins ic_accel_groups/M07_AXI] [get_bd_intf_pins interrupt_manager/s_axi_cfg]
  connect_bd_intf_net -intf_net ic_accel_groups_M08_AXI [get_bd_intf_pins gpio_ack/S_AXI] [get_bd_intf_pins ic_accel_groups/M08_AXI]
  connect_bd_intf_net -intf_net ic_main_M01_AXI [get_bd_intf_pins axi_uartlite/S_AXI] [get_bd_intf_pins ic_main/M01_AXI]
  connect_bd_intf_net -intf_net ic_main_M02_AXI [get_bd_intf_pins ic_main/M02_AXI] [get_bd_intf_pins pcie/S_AXI_CTL]
  connect_bd_intf_net -intf_net ic_main_M03_AXI [get_bd_intf_pins ic_main/M03_AXI] [get_bd_intf_pins ic_pcie_mig/S00_AXI]
  connect_bd_intf_net -intf_net ic_main_M04_AXI [get_bd_intf_pins gpio_pcie_interrupt/S_AXI] [get_bd_intf_pins ic_main/M04_AXI]
  connect_bd_intf_net -intf_net ic_main_M05_AXI [get_bd_intf_pins gpio_msi/S_AXI] [get_bd_intf_pins ic_main/M05_AXI]
  connect_bd_intf_net -intf_net ic_main_M06_AXI [get_bd_intf_pins ic_main/M06_AXI] [get_bd_intf_pins shared_apm/S_AXI]
  connect_bd_intf_net -intf_net ic_main_M07_AXI [get_bd_intf_pins ic_main/M07_AXI] [get_bd_intf_pins shared_metrics_bram_controller/S_AXI]
  connect_bd_intf_net -intf_net ic_main_M08_AXI [get_bd_intf_pins gpio_msi_read/S_AXI] [get_bd_intf_pins ic_main/M08_AXI]
  connect_bd_intf_net -intf_net ic_main_M09_AXI [get_bd_intf_pins ic_accel_groups/S00_AXI] [get_bd_intf_pins ic_main/M09_AXI]
  connect_bd_intf_net -intf_net ic_main_M10_AXI [get_bd_intf_pins cdma_fetch/S_AXI_LITE] [get_bd_intf_pins ic_main/M10_AXI]
  connect_bd_intf_net -intf_net ic_main_M11_AXI [get_bd_intf_pins cdma_send/S_AXI_LITE] [get_bd_intf_pins ic_main/M11_AXI]
  connect_bd_intf_net -intf_net ic_main_M12_AXI [get_bd_intf_pins ic_main/M12_AXI] [get_bd_intf_pins info_memory_block_fetch/s_axi_int_cfg]
  connect_bd_intf_net -intf_net ic_main_M13_AXI [get_bd_intf_pins ic_main/M13_AXI] [get_bd_intf_pins info_memory_block_send/s_axi_int_cfg]
  connect_bd_intf_net -intf_net ic_main_M14_AXI [get_bd_intf_pins fetch_scheduler/s_axi_int_cfg] [get_bd_intf_pins ic_main/M14_AXI]
  connect_bd_intf_net -intf_net ic_main_M15_AXI [get_bd_intf_pins ic_main/M15_AXI] [get_bd_intf_pins send_scheduler/s_axi_int_cfg]
  connect_bd_intf_net -intf_net ic_pcie_mig_M00_AXI [get_bd_intf_pins ic_pcie_mig/M00_AXI] [get_bd_intf_pins pcie/S_AXI]
  connect_bd_intf_net -intf_net ic_pcie_mig_M01_AXI [get_bd_intf_pins ic_pcie_mig/M01_AXI] [get_bd_intf_pins mig/S_AXI]
  connect_bd_intf_net -intf_net interrupt_manager_m_axi_ext_cfg_V [get_bd_intf_pins ic_main/S12_AXI] [get_bd_intf_pins interrupt_manager/m_axi_ext_cfg_V]
  connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins ic_main/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DP]
  connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
  connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_bram/DLMB]
  connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_bram/ILMB]
  connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins axi_interrupt_controller/s_axi] [get_bd_intf_pins ic_main/M00_AXI]
  connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins axi_interrupt_controller/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT]
  connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports ddr3_sdram] [get_bd_intf_pins mig/DDR3]
  connect_bd_intf_net -intf_net pcie_pcie_7x_mgt [get_bd_intf_ports pcie_7x_mgt] [get_bd_intf_pins pcie/pcie_7x_mgt]
  connect_bd_intf_net -intf_net shared_metrics_bram_controller_BRAM_PORTA [get_bd_intf_pins shared_metrics_bram_controller/BRAM_PORTA] [get_bd_intf_pins shared_metrics_bram_controller_bram/BRAM_PORTA]
  connect_bd_intf_net -intf_net sys_diff_clock_1 [get_bd_intf_ports sys_diff_clock] [get_bd_intf_pins clocking_wizard/CLK_IN1_D]

  # Create port connections
  connect_bd_net -net M02_ACLK_1 [get_bd_pins ic_main/M02_ACLK] [get_bd_pins pcie/axi_ctl_aclk_out]
  connect_bd_net -net REFCLK_1 [get_bd_ports REFCLK] [get_bd_pins pcie/REFCLK]
  connect_bd_net -net accel_group_direct_1_dma_intr_in_V [get_bd_pins accel_group_direct_1/dma_intr_in_V] [get_bd_pins xlconcat/In3]
  connect_bd_net -net accel_group_direct_1_interrupt [get_bd_pins accel_group_direct_1/interrupt] [get_bd_pins xlconcat/In4]
  connect_bd_net -net accel_group_indirect_0_interrupt [get_bd_pins accel_group_indirect_0/interrupt] [get_bd_pins xlconcat/In10]
  connect_bd_net -net accel_group_indirect_0_s2mm_introut [get_bd_pins accel_group_indirect_0/s2mm_introut] [get_bd_pins xlconcat/In9]
  connect_bd_net -net accel_group_indirect_1_interrupt [get_bd_pins accel_group_indirect_1/interrupt] [get_bd_pins xlconcat/In12]
  connect_bd_net -net accel_group_indirect_1_s2mm_introut [get_bd_pins accel_group_indirect_1/s2mm_introut] [get_bd_pins xlconcat/In11]
  connect_bd_net -net accel_group_indirect_2_interrupt [get_bd_pins accel_group_indirect_2/interrupt] [get_bd_pins xlconcat/In14]
  connect_bd_net -net accel_group_indirect_2_s2mm_introut [get_bd_pins accel_group_indirect_2/s2mm_introut] [get_bd_pins xlconcat/In13]
  connect_bd_net -net accel_group_indirect_3_interrupt [get_bd_pins accel_group_indirect_3/interrupt] [get_bd_pins xlconcat/In16]
  connect_bd_net -net accel_group_indirect_3_s2mm_introut [get_bd_pins accel_group_indirect_3/s2mm_introut] [get_bd_pins xlconcat/In15]
  connect_bd_net -net accel_group_sg_interrupt [get_bd_pins accel_group_sg/interrupt] [get_bd_pins xlconcat/In18]
  connect_bd_net -net accel_group_sg_interrupt1 [get_bd_pins accel_group_sg/interrupt1] [get_bd_pins xlconcat/In19]
  connect_bd_net -net accel_group_sg_s2mm_introut [get_bd_pins accel_group_sg/s2mm_introut] [get_bd_pins xlconcat/In17]
  connect_bd_net -net acceleration_scheduler_direct_interrupt [get_bd_pins accel_group_direct_0/interrupt] [get_bd_pins xlconcat/In2]
  connect_bd_net -net aux_reset_in_1 [get_bd_ports perst] [get_bd_pins psr_mig/aux_reset_in] [get_bd_pins psr_pcie/aux_reset_in]
  connect_bd_net -net cdma_fetch_cdma_introut [get_bd_pins cdma_fetch/cdma_introut] [get_bd_pins fetch_scheduler/cdma_intr_in_V] [get_bd_pins xlconcat/In5]
  connect_bd_net -net cdma_send_cdma_introut [get_bd_pins cdma_send/cdma_introut] [get_bd_pins send_scheduler/cdma_intr_in_V] [get_bd_pins xlconcat/In6]
  connect_bd_net -net clk_wiz_1_locked [get_bd_pins clocking_wizard/locked] [get_bd_pins psr_main/dcm_locked]
  connect_bd_net -net clocking_wizard_clk_out2 [get_bd_pins clocking_wizard/clk_out2] [get_bd_pins mig/sys_clk_i]
  connect_bd_net -net dma_s2mm_introut [get_bd_pins accel_group_direct_0/dma_intr_in_V] [get_bd_pins xlconcat/In1]
  connect_bd_net -net fetch_scheduler_interrupt [get_bd_pins fetch_scheduler/interrupt] [get_bd_pins xlconcat/In7]
  connect_bd_net -net fetch_scheduler_start_0_V [get_bd_pins accel_group_indirect_0/start_V] [get_bd_pins fetch_scheduler/start_0_V]
  connect_bd_net -net gpio_ack_gpio_io_o [get_bd_pins gpio_ack/gpio_io_o] [get_bd_pins interrupt_manager/intr_ack_V]
  connect_bd_net -net gpio_msi_gpio2_io_o [get_bd_pins gpio_msi/gpio2_io_o] [get_bd_pins gpio_msi_read/gpio_io_i] [get_bd_pins pcie/MSI_Vector_Num]
  connect_bd_net -net gpio_msi_gpio_io_o [get_bd_pins gpio_msi/gpio_io_o] [get_bd_pins pcie/INTX_MSI_Request]
  connect_bd_net -net gpio_pcie_interrupt_gpio_io_o [get_bd_pins gpio_pcie_interrupt/gpio2_io_i] [get_bd_pins gpio_pcie_interrupt/gpio_io_o]
  connect_bd_net -net gpio_pcie_interrupt_ip2intc_irpt [get_bd_pins gpio_pcie_interrupt/ip2intc_irpt] [get_bd_pins xlconcat/In0]
  connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm/Debug_SYS_Rst] [get_bd_pins psr_main/mb_debug_sys_rst]
  connect_bd_net -net microblaze_0_Clk [get_bd_pins accel_group_direct_0/ACLK] [get_bd_pins accel_group_direct_1/ACLK] [get_bd_pins accel_group_indirect_0/ACLK] [get_bd_pins accel_group_indirect_1/ACLK] [get_bd_pins accel_group_indirect_2/ACLK] [get_bd_pins accel_group_indirect_3/ACLK] [get_bd_pins accel_group_sg/ACLK] [get_bd_pins axi_interrupt_controller/processor_clk] [get_bd_pins axi_interrupt_controller/s_axi_aclk] [get_bd_pins axi_uartlite/s_axi_aclk] [get_bd_pins cdma_fetch/m_axi_aclk] [get_bd_pins cdma_fetch/s_axi_lite_aclk] [get_bd_pins cdma_send/m_axi_aclk] [get_bd_pins cdma_send/s_axi_lite_aclk] [get_bd_pins clocking_wizard/clk_out1] [get_bd_pins fetch_scheduler/ap_clk] [get_bd_pins gpio_ack/s_axi_aclk] [get_bd_pins gpio_msi_read/s_axi_aclk] [get_bd_pins gpio_pcie_interrupt/s_axi_aclk] [get_bd_pins ic_accel_groups/ACLK] [get_bd_pins ic_accel_groups/M00_ACLK] [get_bd_pins ic_accel_groups/M01_ACLK] [get_bd_pins ic_accel_groups/M02_ACLK] [get_bd_pins ic_accel_groups/M03_ACLK] [get_bd_pins ic_accel_groups/M04_ACLK] [get_bd_pins ic_accel_groups/M05_ACLK] [get_bd_pins ic_accel_groups/M06_ACLK] [get_bd_pins ic_accel_groups/M07_ACLK] [get_bd_pins ic_accel_groups/M08_ACLK] [get_bd_pins ic_accel_groups/S00_ACLK] [get_bd_pins ic_dmas/ACLK] [get_bd_pins ic_dmas/M00_ACLK] [get_bd_pins ic_dmas/S00_ACLK] [get_bd_pins ic_dmas/S01_ACLK] [get_bd_pins ic_dmas/S02_ACLK] [get_bd_pins ic_dmas/S03_ACLK] [get_bd_pins ic_dmas/S04_ACLK] [get_bd_pins ic_dmas/S05_ACLK] [get_bd_pins ic_dmas/S06_ACLK] [get_bd_pins ic_dmas/S07_ACLK] [get_bd_pins ic_dmas/S08_ACLK] [get_bd_pins ic_dmas/S09_ACLK] [get_bd_pins ic_dmas/S10_ACLK] [get_bd_pins ic_dmas/S11_ACLK] [get_bd_pins ic_dmas/S12_ACLK] [get_bd_pins ic_dmas/S13_ACLK] [get_bd_pins ic_main/ACLK] [get_bd_pins ic_main/M00_ACLK] [get_bd_pins ic_main/M01_ACLK] [get_bd_pins ic_main/M03_ACLK] [get_bd_pins ic_main/M04_ACLK] [get_bd_pins ic_main/M06_ACLK] [get_bd_pins ic_main/M07_ACLK] [get_bd_pins ic_main/M08_ACLK] [get_bd_pins ic_main/M09_ACLK] [get_bd_pins ic_main/M10_ACLK] [get_bd_pins ic_main/M11_ACLK] [get_bd_pins ic_main/M12_ACLK] [get_bd_pins ic_main/M13_ACLK] [get_bd_pins ic_main/M14_ACLK] [get_bd_pins ic_main/M15_ACLK] [get_bd_pins ic_main/S00_ACLK] [get_bd_pins ic_main/S02_ACLK] [get_bd_pins ic_main/S03_ACLK] [get_bd_pins ic_main/S04_ACLK] [get_bd_pins ic_main/S05_ACLK] [get_bd_pins ic_main/S06_ACLK] [get_bd_pins ic_main/S07_ACLK] [get_bd_pins ic_main/S08_ACLK] [get_bd_pins ic_main/S09_ACLK] [get_bd_pins ic_main/S10_ACLK] [get_bd_pins ic_main/S11_ACLK] [get_bd_pins ic_main/S12_ACLK] [get_bd_pins ic_pcie_mig/ACLK] [get_bd_pins ic_pcie_mig/S00_ACLK] [get_bd_pins ic_pcie_mig/S01_ACLK] [get_bd_pins ic_pcie_mig/S02_ACLK] [get_bd_pins ic_pcie_mig/S03_ACLK] [get_bd_pins interrupt_manager/ap_clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_bram/LMB_Clk] [get_bd_pins psr_main/slowest_sync_clk] [get_bd_pins info_memory_block_fetch/ap_clk] [get_bd_pins info_memory_block_send/ap_clk] [get_bd_pins send_scheduler/ap_clk] [get_bd_pins shared_apm/core_aclk] [get_bd_pins shared_apm/s_axi_aclk] [get_bd_pins shared_apm/slot_0_axi_aclk] [get_bd_pins shared_metrics_bram_controller/s_axi_aclk]
  connect_bd_net -net microblaze_0_intr [get_bd_pins axi_interrupt_controller/intr] [get_bd_pins xlconcat/dout]
  connect_bd_net -net mig_init_calib_complete [get_bd_ports init_calib_complete] [get_bd_pins mig/init_calib_complete]
  connect_bd_net -net mig_mmcm_locked [get_bd_pins mig/mmcm_locked] [get_bd_pins psr_mig/dcm_locked]
  connect_bd_net -net mig_ui_clk [get_bd_pins ic_pcie_mig/M01_ACLK] [get_bd_pins mig/ui_clk] [get_bd_pins psr_mig/slowest_sync_clk]
  connect_bd_net -net pcie_axi_aclk_out [get_bd_pins gpio_msi/s_axi_aclk] [get_bd_pins ic_main/M05_ACLK] [get_bd_pins ic_main/S01_ACLK] [get_bd_pins ic_pcie_mig/M00_ACLK] [get_bd_pins pcie/axi_aclk_out] [get_bd_pins psr_pcie/slowest_sync_clk]
  connect_bd_net -net pcie_mmcm_lock [get_bd_pins pcie/mmcm_lock] [get_bd_pins psr_pcie/dcm_locked]
  connect_bd_net -net psr_mig_interconnect_aresetn [get_bd_pins ic_pcie_mig/M01_ARESETN] [get_bd_pins mig/aresetn] [get_bd_pins psr_mig/interconnect_aresetn]
  connect_bd_net -net psr_pcie_interconnect_aresetn [get_bd_pins ic_main/M02_ARESETN] [get_bd_pins ic_main/S01_ARESETN] [get_bd_pins ic_pcie_mig/M00_ARESETN] [get_bd_pins pcie/axi_aresetn] [get_bd_pins psr_pcie/interconnect_aresetn]
  connect_bd_net -net psr_pcie_peripheral_aresetn [get_bd_pins gpio_msi/s_axi_aresetn] [get_bd_pins ic_main/M05_ARESETN] [get_bd_pins psr_pcie/peripheral_aresetn]
  connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins clocking_wizard/reset] [get_bd_pins mig/sys_rst] [get_bd_pins psr_main/ext_reset_in] [get_bd_pins psr_mig/ext_reset_in] [get_bd_pins psr_pcie/ext_reset_in]
  connect_bd_net -net rst_clk_wiz_1_100M_bus_struct_reset [get_bd_pins microblaze_bram/SYS_Rst] [get_bd_pins psr_main/bus_struct_reset]
  connect_bd_net -net rst_clk_wiz_1_100M_interconnect_aresetn [get_bd_pins accel_group_direct_0/ARESETN] [get_bd_pins accel_group_direct_1/ARESETN] [get_bd_pins accel_group_indirect_0/ARESETN] [get_bd_pins accel_group_indirect_1/ARESETN] [get_bd_pins accel_group_indirect_2/ARESETN] [get_bd_pins accel_group_indirect_3/ARESETN] [get_bd_pins accel_group_sg/ARESETN] [get_bd_pins ic_accel_groups/ARESETN] [get_bd_pins ic_dmas/ARESETN] [get_bd_pins ic_main/ARESETN] [get_bd_pins ic_pcie_mig/ARESETN] [get_bd_pins psr_main/interconnect_aresetn]
  connect_bd_net -net rst_clk_wiz_1_100M_mb_reset [get_bd_pins axi_interrupt_controller/processor_rst] [get_bd_pins microblaze_0/Reset] [get_bd_pins psr_main/mb_reset]
  connect_bd_net -net rst_clk_wiz_1_100M_peripheral_aresetn [get_bd_pins accel_group_direct_0/S00_ARESETN] [get_bd_pins accel_group_direct_1/S00_ARESETN] [get_bd_pins accel_group_indirect_0/S00_ARESETN] [get_bd_pins accel_group_indirect_1/S00_ARESETN] [get_bd_pins accel_group_indirect_2/S00_ARESETN] [get_bd_pins accel_group_indirect_3/S00_ARESETN] [get_bd_pins accel_group_sg/S00_ARESETN] [get_bd_pins axi_interrupt_controller/s_axi_aresetn] [get_bd_pins axi_uartlite/s_axi_aresetn] [get_bd_pins cdma_fetch/s_axi_lite_aresetn] [get_bd_pins cdma_send/s_axi_lite_aresetn] [get_bd_pins fetch_scheduler/ap_rst_n] [get_bd_pins gpio_ack/s_axi_aresetn] [get_bd_pins gpio_msi_read/s_axi_aresetn] [get_bd_pins gpio_pcie_interrupt/s_axi_aresetn] [get_bd_pins ic_accel_groups/M00_ARESETN] [get_bd_pins ic_accel_groups/M01_ARESETN] [get_bd_pins ic_accel_groups/M02_ARESETN] [get_bd_pins ic_accel_groups/M03_ARESETN] [get_bd_pins ic_accel_groups/M04_ARESETN] [get_bd_pins ic_accel_groups/M05_ARESETN] [get_bd_pins ic_accel_groups/M06_ARESETN] [get_bd_pins ic_accel_groups/M07_ARESETN] [get_bd_pins ic_accel_groups/M08_ARESETN] [get_bd_pins ic_accel_groups/S00_ARESETN] [get_bd_pins ic_dmas/M00_ARESETN] [get_bd_pins ic_dmas/S00_ARESETN] [get_bd_pins ic_dmas/S01_ARESETN] [get_bd_pins ic_dmas/S02_ARESETN] [get_bd_pins ic_dmas/S03_ARESETN] [get_bd_pins ic_dmas/S04_ARESETN] [get_bd_pins ic_dmas/S05_ARESETN] [get_bd_pins ic_dmas/S06_ARESETN] [get_bd_pins ic_dmas/S07_ARESETN] [get_bd_pins ic_dmas/S08_ARESETN] [get_bd_pins ic_dmas/S09_ARESETN] [get_bd_pins ic_dmas/S10_ARESETN] [get_bd_pins ic_dmas/S11_ARESETN] [get_bd_pins ic_dmas/S12_ARESETN] [get_bd_pins ic_dmas/S13_ARESETN] [get_bd_pins ic_main/M00_ARESETN] [get_bd_pins ic_main/M01_ARESETN] [get_bd_pins ic_main/M03_ARESETN] [get_bd_pins ic_main/M04_ARESETN] [get_bd_pins ic_main/M06_ARESETN] [get_bd_pins ic_main/M07_ARESETN] [get_bd_pins ic_main/M08_ARESETN] [get_bd_pins ic_main/M09_ARESETN] [get_bd_pins ic_main/M10_ARESETN] [get_bd_pins ic_main/M11_ARESETN] [get_bd_pins ic_main/M12_ARESETN] [get_bd_pins ic_main/M13_ARESETN] [get_bd_pins ic_main/M14_ARESETN] [get_bd_pins ic_main/M15_ARESETN] [get_bd_pins ic_main/S00_ARESETN] [get_bd_pins ic_main/S02_ARESETN] [get_bd_pins ic_main/S03_ARESETN] [get_bd_pins ic_main/S04_ARESETN] [get_bd_pins ic_main/S05_ARESETN] [get_bd_pins ic_main/S06_ARESETN] [get_bd_pins ic_main/S07_ARESETN] [get_bd_pins ic_main/S08_ARESETN] [get_bd_pins ic_main/S09_ARESETN] [get_bd_pins ic_main/S10_ARESETN] [get_bd_pins ic_main/S11_ARESETN] [get_bd_pins ic_main/S12_ARESETN] [get_bd_pins ic_pcie_mig/S00_ARESETN] [get_bd_pins ic_pcie_mig/S01_ARESETN] [get_bd_pins ic_pcie_mig/S02_ARESETN] [get_bd_pins ic_pcie_mig/S03_ARESETN] [get_bd_pins interrupt_manager/ap_rst_n] [get_bd_pins psr_main/peripheral_aresetn] [get_bd_pins info_memory_block_fetch/ap_rst_n] [get_bd_pins info_memory_block_send/ap_rst_n] [get_bd_pins send_scheduler/ap_rst_n] [get_bd_pins shared_apm/core_aresetn] [get_bd_pins shared_apm/s_axi_aresetn] [get_bd_pins shared_apm/slot_0_axi_aresetn] [get_bd_pins shared_metrics_bram_controller/s_axi_aresetn]
  connect_bd_net -net send_scheduler_interrupt [get_bd_pins send_scheduler/interrupt] [get_bd_pins xlconcat/In8]
  connect_bd_net -net start_V_1 [get_bd_pins accel_group_indirect_1/start_V] [get_bd_pins fetch_scheduler/start_1_V]
  connect_bd_net -net start_V_2 [get_bd_pins accel_group_indirect_2/start_V] [get_bd_pins fetch_scheduler/start_2_V]
  connect_bd_net -net start_V_3 [get_bd_pins accel_group_indirect_3/start_V] [get_bd_pins fetch_scheduler/start_3_V]

  # Create address segments
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces cdma_fetch/Data] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces cdma_send/Data] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg19
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg23
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg27
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg11
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces fetch_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg31
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg22
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg30
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg38
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg24
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg32
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg40
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg47
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg11
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg18
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg26
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg34
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg42
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg49
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg20
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg28
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg36
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg44
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces interrupt_manager/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg52
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg20
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_bram/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg20
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x40000 -offset 0x0 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_bram/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_microblaze_0_axi_intc_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg12
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg15
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg17
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces pcie/M_AXI] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg12
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg21
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg25
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg29
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg11
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces send_scheduler/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg33
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_direct_0/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg12
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_direct_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg15
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg17
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg11
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_direct_1/acceleration_scheduler_direct/Data_m_axi_mm2s_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg19
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_direct_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg15
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg22
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg6
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg17
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg24
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg10
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg19
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_indirect_0/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg26
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_0/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg17
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg31
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg18
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg19
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg25
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg33
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg20
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg21
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg27
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg35
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg22
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg23
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg29
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_indirect_1/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg37
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_1/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg1
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg31
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg39
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg3
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg18
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg25
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg33
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg41
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg5
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg20
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg27
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg35
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg43
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg8
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg22
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg29
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg37
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_indirect_2/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg45
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_2/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg16
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg31
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg39
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg47
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg2
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg18
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg25
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg33
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg41
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg49
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg4
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg20
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg27
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg35
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg43
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg51
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg7
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg22
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg29
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg37
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg45
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_indirect_3/acceleration_scheduler_indirect/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg53
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_indirect_3/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg9
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg39
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg55
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg71
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg13
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg27
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg43
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg59
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg75
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg89
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg17
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg31
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg47
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg63
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg79
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg93
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg21
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg35
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg51
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg67
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg83
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_sg/acceleration_scheduler_sg_xdma/Data_m_axi_ext_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg99
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_sg/dma/Data_MM2S] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_sg/dma/Data_S2MM] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x100C0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_0/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10100000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_1/acceleration_scheduler_direct/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_direct_Reg11
  create_bd_addr_seg -range 0x10000 -offset 0x10140000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_0/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10180000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_1/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg41
  create_bd_addr_seg -range 0x10000 -offset 0x101C0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_2/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg57
  create_bd_addr_seg -range 0x10000 -offset 0x10200000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_3/acceleration_scheduler_indirect/s_axi_int_cfg/Reg] SEG_acceleration_scheduler_indirect_Reg73
  create_bd_addr_seg -range 0x10000 -offset 0x10240000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_sg/acceleration_scheduler_sg_xdma/s_axi_mm2s_cfg/Reg] SEG_acceleration_scheduler_sg_xdma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100D0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_0/apm/S_AXI/Reg] SEG_apm_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10110000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_1/apm/S_AXI/Reg] SEG_apm_Reg15
  create_bd_addr_seg -range 0x10000 -offset 0x10150000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_0/apm/S_AXI/Reg] SEG_apm_Reg29
  create_bd_addr_seg -range 0x10000 -offset 0x10190000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_1/apm/S_AXI/Reg] SEG_apm_Reg45
  create_bd_addr_seg -range 0x10000 -offset 0x101D0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_2/apm/S_AXI/Reg] SEG_apm_Reg61
  create_bd_addr_seg -range 0x10000 -offset 0x10210000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_3/apm/S_AXI/Reg] SEG_apm_Reg77
  create_bd_addr_seg -range 0x10000 -offset 0x10250000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_sg/apm/S_AXI/Reg] SEG_apm_Reg91
  create_bd_addr_seg -range 0x10000 -offset 0x10000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs axi_interrupt_controller/s_axi/Reg] SEG_axi_interrupt_controller_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10010000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs axi_uartlite/S_AXI/Reg] SEG_axi_uartlite_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100A0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs cdma_fetch/S_AXI_LITE/Reg] SEG_cdma_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100B0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs cdma_send/S_AXI_LITE/Reg] SEG_cdma_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x100E0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10120000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg19
  create_bd_addr_seg -range 0x10000 -offset 0x10160000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_0/dma/S_AXI_LITE/Reg] SEG_dma_Reg33
  create_bd_addr_seg -range 0x10000 -offset 0x101A0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_1/dma/S_AXI_LITE/Reg] SEG_dma_Reg49
  create_bd_addr_seg -range 0x10000 -offset 0x101E0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_2/dma/S_AXI_LITE/Reg] SEG_dma_Reg65
  create_bd_addr_seg -range 0x10000 -offset 0x10220000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_3/dma/S_AXI_LITE/Reg] SEG_dma_Reg81
  create_bd_addr_seg -range 0x10000 -offset 0x10290000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_sg/dma/S_AXI_LITE/Reg] SEG_dma_Reg95
  create_bd_addr_seg -range 0x10000 -offset 0x10260000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_sg/dma_sg_pcie_scheduler/s_axi_cfg/Reg] SEG_dma_sg_pcie_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10060000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs fetch_scheduler/s_axi_int_cfg/Reg] SEG_fetch_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10320000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs gpio_ack/S_AXI/Reg] SEG_gpio_ack_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10040000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs gpio_msi/S_AXI/Reg] SEG_gpio_msi_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10300000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs gpio_msi_read/S_AXI/Reg] SEG_gpio_msi_read_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10030000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs gpio_pcie_interrupt/S_AXI/Reg] SEG_gpio_pcie_interrupt_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10310000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs interrupt_manager/s_axi_cfg/Reg] SEG_interrupt_manager_Reg
  create_bd_addr_seg -range 0x20000000 -offset 0x80000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs mig/memmap/memaddr] SEG_mig_memaddr
  create_bd_addr_seg -range 0x400000 -offset 0x20000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR0] SEG_pcie_BAR0
  create_bd_addr_seg -range 0x400000 -offset 0x30000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR1] SEG_pcie_BAR1
  create_bd_addr_seg -range 0x400000 -offset 0x40000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR2] SEG_pcie_BAR2
  create_bd_addr_seg -range 0x400000 -offset 0x50000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR3] SEG_pcie_BAR3
  create_bd_addr_seg -range 0x1000 -offset 0x60000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR4] SEG_pcie_BAR4
  create_bd_addr_seg -range 0x1000 -offset 0x70000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI/BAR5] SEG_pcie_BAR5
  create_bd_addr_seg -range 0x10000 -offset 0x10020000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs pcie/S_AXI_CTL/CTL0] SEG_pcie_CTL0
  create_bd_addr_seg -range 0x10000 -offset 0x10080000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs info_memory_block_fetch/s_axi_int_cfg/Reg] SEG_info_memory_block_fetch_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10090000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs info_memory_block_send/s_axi_int_cfg/Reg] SEG_info_memory_block_send_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10070000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs send_scheduler/s_axi_int_cfg/Reg] SEG_send_scheduler_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10050000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs shared_apm/S_AXI/Reg] SEG_shared_apm_Reg
  create_bd_addr_seg -range 0x40000 -offset 0xC0000000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs shared_metrics_bram_controller/S_AXI/Mem0] SEG_shared_metrics_bram_controller_Mem0
  create_bd_addr_seg -range 0x10000 -offset 0x100F0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg
  create_bd_addr_seg -range 0x10000 -offset 0x10130000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_direct_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg23
  create_bd_addr_seg -range 0x10000 -offset 0x10170000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_0/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg37
  create_bd_addr_seg -range 0x10000 -offset 0x101B0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_1/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg53
  create_bd_addr_seg -range 0x10000 -offset 0x101F0000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_2/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg69
  create_bd_addr_seg -range 0x10000 -offset 0x10230000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_indirect_3/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg85
  create_bd_addr_seg -range 0x10000 -offset 0x10280000 [get_bd_addr_spaces accel_group_sg/dma_sg_pcie_scheduler/Data_m_axi_cfg_V] [get_bd_addr_segs accel_group_sg/sobel_filter/s_axi_S_AXI4_LITE/Reg] SEG_sobel_filter_Reg101

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   guistr: "# # String gsaved with Nlview 6.5.5  2015-06-26 bk=1.3371 VDI=38 GEI=35 GUI=JA:1.8
#  -string -flagsOSRD
preplace port ddr3_sdram -pg 1 -y 2160 -defaultsOSRD
preplace port perst -pg 1 -y 2580 -defaultsOSRD
preplace port rs232_uart -pg 1 -y 1980 -defaultsOSRD
preplace port REFCLK -pg 1 -y 1960 -defaultsOSRD
preplace port init_calib_complete -pg 1 -y 2240 -defaultsOSRD
preplace port reset -pg 1 -y 2520 -defaultsOSRD
preplace port pcie_7x_mgt -pg 1 -y 2200 -defaultsOSRD
preplace port sys_diff_clock -pg 1 -y 2500 -defaultsOSRD
preplace inst accel_group_direct_1 -pg 1 -lvl 4 -y 540 -defaultsOSRD
preplace inst ic_dmas -pg 1 -lvl 6 -y 1350 -defaultsOSRD
preplace inst psr_pcie -pg 1 -lvl 3 -y 2050 -defaultsOSRD
preplace inst interrupt_manager -pg 1 -lvl 2 -y 1700 -defaultsOSRD
preplace inst shared_metrics_bram_controller -pg 1 -lvl 6 -y 3614 -defaultsOSRD
preplace inst shared_apm -pg 1 -lvl 6 -y 3074 -defaultsOSRD
preplace inst mdm -pg 1 -lvl 3 -y 2390 -defaultsOSRD
preplace inst cdma_fetch -pg 1 -lvl 6 -y 2224 -defaultsOSRD
preplace inst mig -pg 1 -lvl 8 -y 2200 -defaultsOSRD
preplace inst shared_metrics_bram_controller_bram -pg 1 -lvl 7 -y 2970 -defaultsOSRD
preplace inst clocking_wizard -pg 1 -lvl 1 -y 2510 -defaultsOSRD
preplace inst axi_interrupt_controller -pg 1 -lvl 3 -y 2240 -defaultsOSRD
preplace inst pcie -pg 1 -lvl 4 -y 2260 -defaultsOSRD
preplace inst axi_uartlite -pg 1 -lvl 8 -y 1990 -defaultsOSRD
preplace inst ic_main -pg 1 -lvl 5 -y 1500 -defaultsOSRD
preplace inst info_memory_block_fetch -pg 1 -lvl 6 -y 2844 -defaultsOSRD
preplace inst accel_group_indirect_0 -pg 1 -lvl 4 -y 1110 -defaultsOSRD
preplace inst gpio_msi_read -pg 1 -lvl 6 -y 2524 -defaultsOSRD
preplace inst xlconcat -pg 1 -lvl 2 -y 790 -defaultsOSRD
preplace inst accel_group_indirect_1 -pg 1 -lvl 4 -y 1360 -defaultsOSRD
preplace inst psr_mig -pg 1 -lvl 6 -y 3454 -defaultsOSRD
preplace inst fetch_scheduler -pg 1 -lvl 4 -y 100 -defaultsOSRD
preplace inst accel_group_indirect_2 -pg 1 -lvl 4 -y 1616 -defaultsOSRD
preplace inst ic_accel_groups -pg 1 -lvl 3 -y 1660 -defaultsOSRD
preplace inst microblaze_0 -pg 1 -lvl 4 -y 2460 -defaultsOSRD
preplace inst accel_group_sg -pg 1 -lvl 4 -y 2010 -defaultsOSRD
preplace inst accel_group_indirect_3 -pg 1 -lvl 4 -y 1790 -defaultsOSRD
preplace inst cdma_send -pg 1 -lvl 6 -y 2704 -defaultsOSRD
preplace inst gpio_pcie_interrupt -pg 1 -lvl 6 -y 2034 -defaultsOSRD
preplace inst ic_pcie_mig -pg 1 -lvl 7 -y 2160 -defaultsOSRD
preplace inst send_scheduler -pg 1 -lvl 4 -y 360 -defaultsOSRD
preplace inst gpio_ack -pg 1 -lvl 2 -y 1860 -defaultsOSRD
preplace inst psr_main -pg 1 -lvl 2 -y 2470 -defaultsOSRD
preplace inst microblaze_bram -pg 1 -lvl 5 -y 2410 -defaultsOSRD
preplace inst info_memory_block_send -pg 1 -lvl 6 -y 3284 -defaultsOSRD
preplace inst accel_group_direct_0 -pg 1 -lvl 4 -y 770 -defaultsOSRD
preplace inst gpio_msi -pg 1 -lvl 6 -y 2384 -defaultsOSRD
preplace netloc S05_AXI_2 1 4 2 NJ 670 NJ
preplace netloc mig_7series_0_DDR3 1 8 1 NJ
preplace netloc acceleration_scheduler_direct_interrupt 1 1 4 310 490 NJ 490 NJ 860 2040
preplace netloc ic_main_M05_AXI 1 5 1 2910
preplace netloc S10_AXI_1 1 4 1 2410
preplace netloc ic_main_M08_AXI 1 5 1 2890
preplace netloc ic_main_M06_AXI 1 5 1 2880
preplace netloc gpio_msi_gpio2_io_o 1 3 4 1430 2630 NJ 2630 NJ 2610 3460
preplace netloc sys_diff_clock_1 1 0 1 NJ
preplace netloc accel_group_indirect_3_M_AXI_MM2S 1 4 2 2270 640 NJ
preplace netloc accel_group_indirect_1_M_AXI_S2MM 1 4 2 NJ 620 NJ
preplace netloc ic_main_M04_AXI 1 5 1 2920
preplace netloc axi_uartlite_UART 1 8 1 NJ
preplace netloc clocking_wizard_clk_out2 1 1 7 NJ 2370 NJ 2460 NJ 2590 NJ 2590 NJ 1860 NJ 1860 NJ
preplace netloc psr_pcie_interconnect_aresetn 1 3 4 1260 2560 2440 2290 NJ 2140 NJ
preplace netloc accel_group_indirect_0_interrupt 1 1 4 270 1210 NJ 1210 NJ 1210 NJ
preplace netloc cdma_send_cdma_introut 1 1 6 260 440 NJ 440 1220 440 NJ 440 NJ 440 3490
preplace netloc mig_mmcm_locked 1 5 4 NJ 1870 NJ 1850 NJ 1850 5300
preplace netloc ic_accel_groups_M06_AXI 1 3 1 1310
preplace netloc accel_group_indirect_1_m_axi_ext_cfg_V 1 4 1 2360
preplace netloc ic_main_M14_AXI 1 3 3 1430 240 NJ 240 2830
preplace netloc ic_accel_groups_M01_AXI 1 3 1 1250
preplace netloc psr_pcie_peripheral_aresetn 1 3 3 NJ 2540 2450 2490 NJ
preplace netloc gpio_pcie_interrupt_ip2intc_irpt 1 1 6 350 540 NJ 540 NJ 630 NJ 550 NJ 550 3470
preplace netloc microblaze_0_dlmb_1 1 4 1 2430
preplace netloc microblaze_0_intc_axi 1 2 4 870 270 NJ 270 NJ 270 2800
preplace netloc rst_clk_wiz_1_100M_mb_reset 1 2 2 850 2490 N
preplace netloc ic_main_M13_AXI 1 5 1 2840
preplace netloc accel_group_indirect_1_interrupt 1 1 4 290 1220 NJ 1220 NJ 1220 2040
preplace netloc cdma_fetch_cdma_introut 1 1 6 300 500 NJ 500 1420 640 NJ 540 NJ 540 3480
preplace netloc psr_mig_interconnect_aresetn 1 6 2 3550 1930 NJ
preplace netloc ic_main_M10_AXI 1 5 1 2900
preplace netloc accel_group_direct_1_interrupt 1 1 4 270 480 NJ 480 NJ 660 2040
preplace netloc ic_accel_groups_M05_AXI 1 3 1 1320
preplace netloc accel_group_direct_1_M_AXI_S2MM 1 4 2 NJ 520 3080
preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 2 3 NJ 2500 NJ 2550 2480
preplace netloc accel_group_sg_s2mm_introut 1 1 4 250 2580 NJ 2580 NJ 2580 2050
preplace netloc S01_AXI_1 1 4 1 2180
preplace netloc ic_main_M03_AXI 1 5 2 NJ 840 NJ
preplace netloc pcie_axi_aclk_out 1 2 5 860 2600 NJ 2600 2470 2520 2800 2600 NJ
preplace netloc S01_AXI_2 1 4 2 NJ 660 NJ
preplace netloc ic_main_M12_AXI 1 5 1 2860
preplace netloc S01_AXI_3 1 6 1 3540
preplace netloc ic_main_M09_AXI 1 2 4 860 250 NJ 250 NJ 250 2810
preplace netloc microblaze_0_ilmb_1 1 4 1 2460
preplace netloc accel_group_sg_interrupt 1 1 4 300 1950 NJ 1950 NJ 1890 2040
preplace netloc S09_AXI_1 1 4 2 2280 690 NJ
preplace netloc accel_group_indirect_2_M_AXI_MM2S 1 4 2 NJ 630 NJ
preplace netloc ic_accel_groups_M00_AXI 1 3 1 1260
preplace netloc microblaze_0_interrupt 1 3 1 1290
preplace netloc ic_main_M11_AXI 1 5 1 2870
preplace netloc mdm_1_debug_sys_rst 1 1 3 350 2380 NJ 2450 1230
preplace netloc ic_pcie_mig_M00_AXI 1 3 5 1410 890 NJ 510 NJ 510 NJ 510 4980
preplace netloc pcie_mmcm_lock 1 2 3 880 2570 NJ 2570 2040
preplace netloc accel_group_indirect_0_M_AXI_MM2S 1 4 2 NJ 610 NJ
preplace netloc S02_AXI_1 1 4 1 2330
preplace netloc S02_AXI_2 1 4 2 NJ 490 3090
preplace netloc S02_AXI_3 1 6 1 3500
preplace netloc M02_ACLK_1 1 4 1 2430
preplace netloc ic_accel_groups_M08_AXI 1 1 3 330 1340 NJ 1340 1220
preplace netloc S11_AXI_1 1 4 2 2310 700 NJ
preplace netloc accel_group_indirect_0_s2mm_introut 1 1 4 260 1200 NJ 1200 NJ 1200 NJ
preplace netloc microblaze_0_Clk 1 1 7 220 1620 830 1360 1330 960 2370 580 2930 1940 3590 1920 5010
preplace netloc S11_AXI_2 1 4 1 2420
preplace netloc accel_group_direct_1_dma_intr_in_V 1 1 4 330 510 NJ 510 NJ 670 2050
preplace netloc aux_reset_in_1 1 0 6 NJ 2580 NJ 2590 820 2590 NJ 2610 NJ 2610 NJ
preplace netloc ic_main_M07_AXI 1 5 1 2850
preplace netloc ic_main_M01_AXI 1 5 3 NJ 820 NJ 820 5040
preplace netloc accel_group_indirect_3_m_axi_ext_cfg_V 1 4 1 2390
preplace netloc accel_group_indirect_3_s2mm_introut 1 1 4 350 1040 NJ 1010 NJ 1010 2070
preplace netloc shared_metrics_bram_controller_BRAM_PORTA 1 6 1 NJ
preplace netloc fetch_scheduler_interrupt 1 1 4 320 550 NJ 550 NJ 650 2060
preplace netloc ic_accel_groups_M03_AXI 1 3 1 1300
preplace netloc clk_wiz_1_locked 1 1 1 240
preplace netloc ic_accel_groups_M04_AXI 1 3 1 1310
preplace netloc microblaze_0_debug 1 3 1 1270
preplace netloc gpio_pcie_interrupt_gpio_io_o 1 6 1 3460
preplace netloc interrupt_manager_m_axi_ext_cfg_V 1 2 3 780 990 NJ 990 NJ
preplace netloc microblaze_0_axi_dp 1 4 1 2400
preplace netloc ic_main_M02_AXI 1 3 3 1400 880 NJ 710 2790
preplace netloc ic_accel_groups_M07_AXI 1 1 3 350 1330 NJ 1330 1230
preplace netloc S06_AXI_1 1 4 1 2300
preplace netloc ic_main_M15_AXI 1 3 3 1430 260 NJ 260 2820
preplace netloc rst_clk_wiz_1_100M_interconnect_aresetn 1 2 5 790 1370 1390 910 2380 570 3030 810 3560
preplace netloc S06_AXI_2 1 4 2 2240 680 NJ
preplace netloc fetch_scheduler_start_0_V 1 3 2 1430 900 2070
preplace netloc accel_group_indirect_2_s2mm_introut 1 1 4 340 1030 NJ 970 NJ 970 2080
preplace netloc accel_group_indirect_3_interrupt 1 1 4 280 1940 NJ 1940 NJ 1880 2040
preplace netloc gpio_ack_gpio_io_o 1 1 2 350 1780 750
preplace netloc dma_s2mm_introut 1 1 4 340 520 NJ 520 NJ 870 2050
preplace netloc accel_group_sg_M_AXI_MM2S 1 4 2 2250 590 NJ
preplace netloc accel_group_indirect_2_m_axi_ext_cfg_V 1 4 1 2210
preplace netloc mig_ui_clk 1 5 4 3090 2130 3520 1880 NJ 1880 5290
preplace netloc send_scheduler_interrupt 1 1 4 250 280 NJ 280 NJ 280 2040
preplace netloc S13_AXI_1 1 4 2 2260 600 NJ
preplace netloc S04_AXI_1 1 4 1 2340
preplace netloc ic_pcie_mig_M01_AXI 1 7 1 N
preplace netloc start_V_1 1 3 2 1420 1230 2110
preplace netloc mig_init_calib_complete 1 8 1 NJ
preplace netloc REFCLK_1 1 0 4 NJ 1960 NJ 1960 NJ 1960 NJ
preplace netloc accel_group_indirect_1_s2mm_introut 1 1 4 320 1060 NJ 1060 NJ 980 2060
preplace netloc start_V_2 1 3 2 1430 1240 2100
preplace netloc pcie_pcie_7x_mgt 1 4 5 NJ 2280 NJ 1890 NJ 1890 NJ 1890 NJ
preplace netloc ic_accel_groups_M02_AXI 1 3 1 1280
preplace netloc accel_group_sg_interrupt1 1 1 4 310 2140 NJ 2140 NJ 2130 2040
preplace netloc microblaze_0_intr 1 2 1 810
preplace netloc start_V_3 1 3 2 1430 2120 2120
preplace netloc S03_AXI_1 1 4 1 2130
preplace netloc reset_1 1 0 8 -50 2440 240 2350 840 2470 NJ 2640 NJ 2640 3050 1910 NJ 1910 NJ
preplace netloc accel_group_indirect_2_interrupt 1 1 4 330 1050 NJ 950 NJ 950 2090
preplace netloc S05_AXI_1 1 4 1 2320
preplace netloc S03_AXI_2 1 6 1 3570
preplace netloc S00_AXI_1 1 4 2 NJ 720 NJ
preplace netloc gpio_msi_gpio_io_o 1 3 4 1420 2620 NJ 2620 NJ 2620 3470
preplace netloc rst_clk_wiz_1_100M_peripheral_aresetn 1 1 7 340 1790 800 1380 1360 920 2350 560 2940 1900 3530 1900 NJ
levelinfo -pg 1 -70 115 580 1050 1810 2636 3290 4829 5168 5330 -top -40 -bot 3690
",
}

  # Restore current instance
  current_bd_instance $oldCurInst

  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""


