open_project Send_Scheduler

set_top send_scheduler

add_files send_scheduler.cpp

open_solution "solution1"

#The Part Refers to the Xilinx Virtex 7 VC707 FPGA Development Board
set_part {xc7vx485tffg1761-2}
create_clock -period 10 -name default

csynth_design

export_design -format ip_catalog -display_name "Send Scheduler" -version "3.0"

exit