17 lines
469 B
C
17 lines
469 B
C
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/*
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* ---------------------------------------------------
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* Registers and Offsets of the Xilinx GPIO Peripheral
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* ---------------------------------------------------
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*/
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#define XGPIO_CHANNEL_1_OFFSET 0x0 // GPIO Channel 1 Base Offset.
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#define XGPIO_CHANNEL_2_OFFSET 0x8 // GPIO Channel 2 Base Offset.
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/*
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* GPIO Channel 1 Data Register.
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*
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* The Data Register of GPIO Channel 2 is XGPIO_DATA_OFFSET + XGPIO_CHANNEL_2_OFFSET.
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*/
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#define XGPIO_DATA_OFFSET 0x0
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