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Ayaan Tunio
2025-10-12 14:37:14 -04:00
commit 2effba13fa
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//--------------------------------------------------------------------------------
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
//Date : 2025
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module pcie_acceleration_vc707_design_wrapper
(REFCLK_p,
REFCLK_n,
ddr3_sdram_addr,
ddr3_sdram_ba,
ddr3_sdram_cas_n,
ddr3_sdram_ck_n,
ddr3_sdram_ck_p,
ddr3_sdram_cke,
ddr3_sdram_cs_n,
ddr3_sdram_dm,
ddr3_sdram_dq,
ddr3_sdram_dqs_n,
ddr3_sdram_dqs_p,
ddr3_sdram_odt,
ddr3_sdram_ras_n,
ddr3_sdram_reset_n,
ddr3_sdram_we_n,
init_calib_complete,
pcie_7x_mgt_rxn,
pcie_7x_mgt_rxp,
pcie_7x_mgt_txn,
pcie_7x_mgt_txp,
perst,
reset,
rs232_uart_rxd,
rs232_uart_txd,
sys_diff_clock_clk_n,
sys_diff_clock_clk_p);
input REFCLK_p;
input REFCLK_n;
output [13:0]ddr3_sdram_addr;
output [2:0]ddr3_sdram_ba;
output ddr3_sdram_cas_n;
output [0:0]ddr3_sdram_ck_n;
output [0:0]ddr3_sdram_ck_p;
output [0:0]ddr3_sdram_cke;
output [0:0]ddr3_sdram_cs_n;
output [7:0]ddr3_sdram_dm;
inout [63:0]ddr3_sdram_dq;
inout [7:0]ddr3_sdram_dqs_n;
inout [7:0]ddr3_sdram_dqs_p;
output [0:0]ddr3_sdram_odt;
output ddr3_sdram_ras_n;
output ddr3_sdram_reset_n;
output ddr3_sdram_we_n;
output init_calib_complete;
input [3:0]pcie_7x_mgt_rxn;
input [3:0]pcie_7x_mgt_rxp;
output [3:0]pcie_7x_mgt_txn;
output [3:0]pcie_7x_mgt_txp;
input perst;
input reset;
input rs232_uart_rxd;
output rs232_uart_txd;
input sys_diff_clock_clk_n;
input sys_diff_clock_clk_p;
wire REFCLK_p;
wire REFCLK_n;
wire [13:0]ddr3_sdram_addr;
wire [2:0]ddr3_sdram_ba;
wire ddr3_sdram_cas_n;
wire [0:0]ddr3_sdram_ck_n;
wire [0:0]ddr3_sdram_ck_p;
wire [0:0]ddr3_sdram_cke;
wire [0:0]ddr3_sdram_cs_n;
wire [7:0]ddr3_sdram_dm;
wire [63:0]ddr3_sdram_dq;
wire [7:0]ddr3_sdram_dqs_n;
wire [7:0]ddr3_sdram_dqs_p;
wire [0:0]ddr3_sdram_odt;
wire ddr3_sdram_ras_n;
wire ddr3_sdram_reset_n;
wire ddr3_sdram_we_n;
wire init_calib_complete;
wire [3:0]pcie_7x_mgt_rxn;
wire [3:0]pcie_7x_mgt_rxp;
wire [3:0]pcie_7x_mgt_txn;
wire [3:0]pcie_7x_mgt_txp;
wire perst;
wire reset;
wire rs232_uart_rxd;
wire rs232_uart_txd;
wire sys_diff_clock_clk_n;
wire sys_diff_clock_clk_p;
IBUFDS_GTE2 refclk_ibuf (.O(REFCLK), .ODIV2(), .I(REFCLK_p), .CEB(1'b0), .IB(REFCLK_n));
pcie_acceleration_vc707_design pcie_acceleration_vc707_design_i
(.REFCLK(REFCLK),
.ddr3_sdram_addr(ddr3_sdram_addr),
.ddr3_sdram_ba(ddr3_sdram_ba),
.ddr3_sdram_cas_n(ddr3_sdram_cas_n),
.ddr3_sdram_ck_n(ddr3_sdram_ck_n),
.ddr3_sdram_ck_p(ddr3_sdram_ck_p),
.ddr3_sdram_cke(ddr3_sdram_cke),
.ddr3_sdram_cs_n(ddr3_sdram_cs_n),
.ddr3_sdram_dm(ddr3_sdram_dm),
.ddr3_sdram_dq(ddr3_sdram_dq),
.ddr3_sdram_dqs_n(ddr3_sdram_dqs_n),
.ddr3_sdram_dqs_p(ddr3_sdram_dqs_p),
.ddr3_sdram_odt(ddr3_sdram_odt),
.ddr3_sdram_ras_n(ddr3_sdram_ras_n),
.ddr3_sdram_reset_n(ddr3_sdram_reset_n),
.ddr3_sdram_we_n(ddr3_sdram_we_n),
.init_calib_complete(init_calib_complete),
.pcie_7x_mgt_rxn(pcie_7x_mgt_rxn),
.pcie_7x_mgt_rxp(pcie_7x_mgt_rxp),
.pcie_7x_mgt_txn(pcie_7x_mgt_txn),
.pcie_7x_mgt_txp(pcie_7x_mgt_txp),
.perst(perst),
.reset(reset),
.rs232_uart_rxd(rs232_uart_rxd),
.rs232_uart_txd(rs232_uart_txd),
.sys_diff_clock_clk_n(sys_diff_clock_clk_n),
.sys_diff_clock_clk_p(sys_diff_clock_clk_p));
endmodule