Squash commits for public release

Hardware/Vivado_HLS_IPs/Info_Memory_Block/info_memory_block.cpp

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+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include "ap_int.h"
+#include "ap_utils.h"
+#include "ap_cint.h"
+#include "ap_utils.h"
+#include "ap_int.h"
+#include "info_memory_block.h"
+
+
+/*
+ * info_memory_block()
+ *
+ * The Hardware Funtionality of the Info Memory Block Core.
+ *
+ * The Info Memory Block Core is Used to Aid the Acceleration Procedure of the Acceleration Groups Indirect (AGIs).
+ * It is Accessed by the Acceleration Scheduler Indirect Cores of the AGIs as well as the Fetch and Send Schedulers.
+ *
+ * It Could be Considered as a Block of 16 Registers.
+ * The Registers are Categorized in 4 Groups/Sets with 4 Registers in each Group/Set.
+ *
+ * Every Set of Registers Refers to one of the 4 AGIs.
+ *
+ * Set 0 Refers to AGI0.
+ * Set 1 Refers to AGI1.
+ * Set 2 Refers to AGI2.
+ * Set 3 Refers to AGI3.
+ *
+ * The 4 Registers of Each Set Carry the Following Information:
+ *
+ * Register 0: Source Address.
+ * Register 1: Destination Address.
+ * Register 2: Data Size (Transfer Size).
+ * Register 3: Address Offset.
+ *
+ * If an Acceleration Scheduler Indirect Requests a CDMA Transfer it Writes the Information Above to its own Set of Registers inside the Info Memory Block.
+ * The Fetch or Send Scheduler Reads the Above Information from the Info Memory Block and Starts a CDMA Transfer Accordingly.
+ *
+ * The Function Parameters are the Input Ports/Interfaces of the Core:
+ *
+ * 01 to 16 --> Registers of the Core that are Accessed through the AXI Slave Lite Interface of the Core.
+ */
+int info_memory_block(/*01*/unsigned int src_address_0,
+                     /*02*/unsigned int dst_address_0,
+                     /*03*/unsigned int data_size_0,
+                     /*04*/unsigned int offset_0,
+                     /*05*/unsigned int src_address_1,
+                     /*06*/unsigned int dst_address_1,
+                     /*07*/unsigned int data_size_1,
+                     /*08*/unsigned int offset_1,
+                     /*09*/unsigned int src_address_2,
+                     /*10*/unsigned int dst_address_2,
+                     /*11*/unsigned int data_size_2,
+                     /*12*/unsigned int offset_2,
+                     /*13*/unsigned int src_address_3,
+                     /*14*/unsigned int dst_address_3,
+                     /*15*/unsigned int data_size_3,
+                     /*16*/unsigned int offset_3
+                     )
+{
+
+/*
+ * Source Address, Destination Address, Data Size and Address Offset Registers of the First Group/Set
+ */
+#pragma HLS INTERFACE  s_axilite  port=src_address_0 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=dst_address_0 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=data_size_0 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=offset_0 bundle=int_cfg
+
+/*
+ * Source Address, Destination Address, Data Size and Address Offset Registers of the Second Group/Set
+ */
+#pragma HLS INTERFACE  s_axilite  port=src_address_1 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=dst_address_1 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=data_size_1 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=offset_1 bundle=int_cfg
+
+/*
+ * Source Address, Destination Address, Data Size and Address Offset Registers of the Third Group/Set
+ */
+#pragma HLS INTERFACE  s_axilite  port=src_address_2 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=dst_address_2 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=data_size_2 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=offset_2 bundle=int_cfg
+
+/*
+ * Source Address, Destination Address, Data Size and Address Offset Registers of the Fourth Group/Set
+ */
+#pragma HLS INTERFACE  s_axilite  port=src_address_3 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=dst_address_3 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=data_size_3 bundle=int_cfg
+#pragma HLS INTERFACE  s_axilite  port=offset_3 bundle=int_cfg
+
+#pragma HLS INTERFACE  s_axilite  port=return bundle=int_cfg
+
+
+return 1;
+
+}
+
+

Hardware/Vivado_HLS_IPs/Info_Memory_Block/info_memory_block.h

@@ -0,0 +1,95 @@
+struct image_info
+{
+	ap_uint<32> rows;
+	ap_uint<32> columns;
+	ap_uint<64> size;
+};
+
+struct metrics
+{
+	/*
+	 * AXI Performance Monitor Metrics
+	 */
+	ap_uint<32> apm_read_transactions; //Offset 0 Bytes
+	ap_uint<32> apm_read_bytes; //Offset 4 Bytes
+
+	ap_uint<32> apm_write_transactions; //Offset 8 Bytes
+	ap_uint<32> apm_write_bytes; //Offset 12 Bytes
+
+	ap_uint<32> apm_packets; //Offset 16 Bytes
+	ap_uint<32> apm_bytes; //Offset 20 Bytes
+
+	ap_uint<32> apm_gcc_l; //Offset 24 Bytes
+	ap_uint<32> apm_gcc_u; //Offset 28 Bytes
+
+	ap_uint<32> cdma_fetch_time_start_l; //Offset 32 Bytes
+	ap_uint<32> cdma_fetch_time_start_u; //Offset 36 Bytes
+	ap_uint<32> cdma_fetch_time_end_l; //Offset 40 Bytes
+	ap_uint<32> cdma_fetch_time_end_u; //Offset 44 Bytes
+
+	ap_uint<32> cdma_send_time_start_l; //Offset 48 Bytes
+	ap_uint<32> cdma_send_time_start_u; //Offset 52 Bytes
+	ap_uint<32> cdma_send_time_end_l; //Offset 56 Bytes
+	ap_uint<32> cdma_send_time_end_u; //Offset 60 Bytes
+
+	ap_uint<32> dma_accel_time_start_l; //Offset 64 Bytes
+	ap_uint<32> dma_accel_time_start_u; //Offset 68 Bytes
+	ap_uint<32> dma_accel_time_end_l; //Offset 72 Bytes
+	ap_uint<32> dma_accel_time_end_u; //Offset 76 Bytes
+
+	struct image_info shared_image_info; // Offset 80 Bytes
+
+	/*
+	 * Kernel and Userspace Metrics
+	 */
+
+	ap_uint<64> total_time_start;
+	ap_uint<64> total_time_end;
+
+	ap_uint<64> sleep_time_start;
+	ap_uint<64> sleep_time_end;
+
+	ap_uint<64> preparation_time_start;
+	ap_uint<64> preparation_time_end;
+
+	ap_uint<64> load_time_start;
+	ap_uint<64> load_time_end;
+
+	ap_uint<64> save_time_start;
+	ap_uint<64> save_time_end;
+
+
+};
+
+struct status_flags
+{
+	ap_uint<32> accel_direct_0_occupied_pid;
+	ap_uint<32> accel_direct_1_occupied_pid;
+
+	ap_uint<32> accel_indirect_0_occupied_pid;
+	ap_uint<32> accel_indirect_1_occupied_pid;
+	ap_uint<32> accel_indirect_2_occupied_pid;
+	ap_uint<32> accel_indirect_3_occupied_pid;
+
+	ap_uint<32> accel_sg_0_occupied_pid;
+
+
+	ap_uint<32> accelerator_busy;
+	ap_uint<32> open_modules;
+};
+
+struct shared_repository
+{
+	struct metrics accel_direct_0_shared_metrics;
+	struct metrics accel_direct_1_shared_metrics;
+
+	struct metrics accel_indirect_0_shared_metrics;
+	struct metrics accel_indirect_1_shared_metrics;
+	struct metrics accel_indirect_2_shared_metrics;
+	struct metrics accel_indirect_3_shared_metrics;
+
+	struct metrics accel_sg_0_shared_metrics;
+
+	struct status_flags shared_status_flags;
+
+};

Hardware/Vivado_HLS_IPs/Info_Memory_Block/run_hls.tcl

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+open_project Info_Memory_Block
+
+set_top info_memory_block
+
+add_files info_memory_block.cpp
+
+open_solution "solution1"
+
+#The Part Refers to the Xilinx Virtex 7 VC707 FPGA Development Board
+set_part {xc7vx485tffg1761-2}
+create_clock -period 10 -name default
+
+csynth_design
+
+export_design -format ip_catalog -display_name "Info Memory Block" -version "1.0"
+
+exit