Squash commits for public release

Software/Microblaze_XSDK/src/lscript.ld

@@ -0,0 +1,221 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version:                                 */
+/*                                                                 */
+/* Copyright (c) 2010 Xilinx, Inc.  All rights reserved.           */
+/*                                                                 */
+/* Description : MicroBlaze Linker Script                          */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr : ORIGIN = 0x50, LENGTH = 0x3FFB0
+   pcie : ORIGIN = 0x10020000, LENGTH = 0x10000
+   pcie_AXIBAR_0 : ORIGIN = 0x20000000, LENGTH = 0x400000
+   pcie_AXIBAR_1 : ORIGIN = 0x30000000, LENGTH = 0x400000
+   pcie_AXIBAR_2 : ORIGIN = 0x40000000, LENGTH = 0x400000
+   pcie_AXIBAR_3 : ORIGIN = 0x50000000, LENGTH = 0x400000
+   pcie_AXIBAR_4 : ORIGIN = 0x60000000, LENGTH = 0x1000
+   pcie_AXIBAR_5 : ORIGIN = 0x70000000, LENGTH = 0x1000
+   mig : ORIGIN = 0x80000000, LENGTH = 0x20000000
+   shared_metrics_bram_controller_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x40000
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_start)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.vectors.reset 0x0 : {
+   KEEP (*(.vectors.reset))
+} 
+
+.vectors.sw_exception 0x8 : {
+   KEEP (*(.vectors.sw_exception))
+} 
+
+.vectors.interrupt 0x10 : {
+   KEEP (*(.vectors.interrupt))
+} 
+
+.vectors.hw_exception 0x20 : {
+   KEEP (*(.vectors.hw_exception))
+} 
+
+.text : {
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.init : {
+   KEEP (*(.init))
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.fini : {
+   KEEP (*(.fini))
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   PROVIDE(__DTOR_END__ = .);
+   PROVIDE(___DTORS_END___ = .);
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.sdata2 : {
+   . = ALIGN(8);
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   . = ALIGN(8);
+   __sdata2_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.data : {
+   . = ALIGN(4);
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   __data_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.got : {
+   *(.got)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.got1 : {
+   *(.got1)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.got2 : {
+   *(.got2)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.eh_frame : {
+   *(.eh_frame)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.jcr : {
+   *(.jcr)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.sdata : {
+   . = ALIGN(8);
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.sbss (NOLOAD) : {
+   . = ALIGN(4);
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   . = ALIGN(8);
+   __sbss_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.bss (NOLOAD) : {
+   . = ALIGN(4);
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   . = ALIGN(4);
+   __bss_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(8);
+   _heap = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+.stack (NOLOAD) : {
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(8);
+   _stack = .;
+   __stack = _stack;
+} > microblaze_bram_ilmb_bram_if_cntlr_microblaze_bram_dlmb_bram_if_cntlr
+
+_end = .;
+}
+

Software/Microblaze_XSDK/src/main.c

@@ -0,0 +1,84 @@
+#include "stdio.h"
+#include "string.h"
+#include "stdlib.h"
+#include "platform.h"
+#include "xil_exception.h"
+#include "xparameters.h"
+#include "xstatus.h"
+
+#define KBYTE 1024
+
+/*
+ * Functions Declaration
+ */
+int setup_acceleration_scheduler_sg();
+int setup_dma_sg_schedulers();
+int setup_acceleration_schedulers_direct();
+int setup_acceleration_schedulers_indirect();
+int setup_fetch_scheduler();
+int setup_send_scheduler();
+int setup_scheduler_buffers();
+int setup_cdmas();
+int setup_dmas();
+int setup_apms();
+int setup_shared_apm();
+int setup_gpio();
+int setup_pcie();
+int setup_sobel_filters();
+int setup_interrupt_manager();
+int setup_interrupts();
+
+//The Base Address of the FPGA's BRAM (256K).
+int *bram_base_address = (int *)XPAR_SHARED_METRICS_BRAM_CONTROLLER_S_AXI_BASEADDR;
+
+int main()
+{
+	int repeat;
+
+	//Clear the Terminal Screen.
+    xil_printf("%c[2J",27);
+
+    //Initialize the Platform.
+    init_platform();
+
+    //Clear the FPGA's BRAM.
+    for(repeat = 0; repeat < (256 * KBYTE) / 4; repeat++)
+    {
+    	bram_base_address[repeat] = 0;
+    }
+
+    /*
+     * Setup ALL the Peripherals of the FPGA.
+     */
+    setup_acceleration_schedulers_direct();
+    setup_acceleration_schedulers_indirect();
+    setup_fetch_scheduler();
+    setup_send_scheduler();
+    setup_scheduler_buffers();
+    setup_cdmas();
+    setup_dmas();
+    setup_apms();
+    setup_shared_apm();
+    setup_gpio();
+    setup_pcie();
+    setup_sobel_filters();
+    setup_acceleration_scheduler_sg();
+    setup_dma_sg_schedulers();
+    setup_interrupt_manager();
+
+    //Setup the Interrupt Controller and the Interrupts.
+    setup_interrupts();
+
+    print("\r\n-->System is Ready\r\n");
+
+
+    //Start an Infinite Loop to Keep the System Alive.
+	while(1)
+	{
+
+	}
+
+    return XST_SUCCESS;
+}
+
+

Software/Microblaze_XSDK/src/platform.c

@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+#include "xil_cache.h"
+
+#include "platform_config.h"
+
+/*
+ * Uncomment the following line if ps7 init source files are added in the
+ * source directory for compiling example outside of SDK.
+ */
+/*#include "ps7_init.h"*/
+
+#ifdef STDOUT_IS_16550
+ #include "xuartns550_l.h"
+
+ #define UART_BAUD 9600
+#endif
+
+void
+enable_caches()
+{
+#ifdef __PPC__
+    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
+    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
+#elif __MICROBLAZE__
+#ifdef XPAR_MICROBLAZE_USE_ICACHE
+    Xil_ICacheEnable();
+#endif
+#ifdef XPAR_MICROBLAZE_USE_DCACHE
+    Xil_DCacheEnable();
+#endif
+#endif
+}
+
+void
+disable_caches()
+{
+    Xil_DCacheDisable();
+    Xil_ICacheDisable();
+}
+
+void
+init_uart()
+{
+#ifdef STDOUT_IS_16550
+    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
+    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
+#endif
+#ifdef STDOUT_IS_PS7_UART
+    /* Bootrom/BSP configures PS7 UART to 115200 bps */
+#endif
+}
+
+void
+init_platform()
+{
+    /*
+     * If you want to run this example outside of SDK,
+     * uncomment the following line and also #include "ps7_init.h" at the top.
+     * Make sure that the ps7_init.c and ps7_init.h files are included
+     * along with this example source files for compilation.
+     */
+    /* ps7_init();*/
+    enable_caches();
+    init_uart();
+}
+
+void
+cleanup_platform()
+{
+    disable_caches();
+}

Software/Microblaze_XSDK/src/platform.h

@@ -0,0 +1,41 @@
+/******************************************************************************
+*
+* Copyright (C) 2008 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef __PLATFORM_H_
+#define __PLATFORM_H_
+
+#include "platform_config.h"
+
+void init_platform();
+void cleanup_platform();
+
+#endif

Software/Microblaze_XSDK/src/platform_config.h

@@ -0,0 +1,4 @@
+#ifndef __PLATFORM_CONFIG_H_
+#define __PLATFORM_CONFIG_H_
+
+#endif

Software/Microblaze_XSDK/src/structures.h

@@ -0,0 +1,159 @@
+struct image_info
+{
+	u32 rows;
+	u32 columns;
+	u64 size;
+};
+
+struct metrics
+{
+	/*
+	 * AXI Performance Monitor Metrics
+	 */
+	u32 apm_read_transactions; //Offset 0 Bytes
+	u32 apm_read_bytes; //Offset 4 Bytes
+
+	u32 apm_write_transactions; //Offset 8 Bytes
+	u32 apm_write_bytes; //Offset 12 Bytes
+
+	u32 apm_packets; //Offset 16 Bytes
+	u32 apm_bytes; //Offset 20 Bytes
+
+	u32 apm_gcc_l; //Offset 24 Bytes
+	u32 apm_gcc_u; //Offset 28 Bytes
+
+	u32 cdma_fetch_time_start_l; //Offset 32 Bytes
+	u32 cdma_fetch_time_start_u; //Offset 36 Bytes
+	u32 cdma_fetch_time_end_l; //Offset 40 Bytes
+	u32 cdma_fetch_time_end_u; //Offset 44 Bytes
+
+	u32 cdma_send_time_start_l; //Offset 48 Bytes
+	u32 cdma_send_time_start_u; //Offset 52 Bytes
+	u32 cdma_send_time_end_l; //Offset 56 Bytes
+	u32 cdma_send_time_end_u; //Offset 60 Bytes
+
+	u32 dma_accel_time_start_l; //Offset 64 Bytes
+	u32 dma_accel_time_start_u; //Offset 68 Bytes
+	u32 dma_accel_time_end_l; //Offset 72 Bytes
+	u32 dma_accel_time_end_u; //Offset 76 Bytes
+
+	struct image_info shared_image_info; // Offset 80 Bytes
+
+	/*
+	 * Kernel and Userspace Metrics
+	 */
+
+	u64 total_time_start;
+	u64 total_time_end;
+
+	u64 sleep_time_start;
+	u64 sleep_time_end;
+
+	u64 preparation_time_start;
+	u64 preparation_time_end;
+
+	u64 load_time_start;
+	u64 load_time_end;
+
+	u64 save_time_start;
+	u64 save_time_end;
+
+
+};
+
+struct metrics_per_process
+{
+	/*
+	 * AXI Performance Monitor Metrics
+	 */
+	u32 apm_read_transactions; //Offset 0 Bytes
+	u32 apm_read_bytes; //Offset 4 Bytes
+
+	u32 apm_write_transactions; //Offset 8 Bytes
+	u32 apm_write_bytes; //Offset 12 Bytes
+
+	u32 apm_packets; //Offset 16 Bytes
+	u32 apm_bytes; //Offset 20 Bytes
+
+	u32 apm_gcc_l; //Offset 24 Bytes
+	u32 apm_gcc_u; //Offset 28 Bytes
+
+	u32 cdma_fetch_time_start_l; //Offset 32 Bytes
+	u32 cdma_fetch_time_start_u; //Offset 36 Bytes
+	u32 cdma_fetch_time_end_l; //Offset 40 Bytes
+	u32 cdma_fetch_time_end_u; //Offset 44 Bytes
+
+	u32 cdma_send_time_start_l; //Offset 48 Bytes
+	u32 cdma_send_time_start_u; //Offset 52 Bytes
+	u32 cdma_send_time_end_l; //Offset 56 Bytes
+	u32 cdma_send_time_end_u; //Offset 60 Bytes
+
+	u32 dma_accel_time_start_l; //Offset 64 Bytes
+	u32 dma_accel_time_start_u; //Offset 68 Bytes
+	u32 dma_accel_time_end_l; //Offset 72 Bytes
+	u32 dma_accel_time_end_u; //Offset 76 Bytes
+
+	struct image_info shared_image_info; // Offset 80 Bytes
+
+	/*
+	 * Kernel and Userspace Metrics
+	 */
+
+	u64 total_time_start;
+	u64 total_time_end;
+
+	u64 sleep_time_start;
+	u64 sleep_time_end;
+
+	u64 preparation_time_start;
+	u64 preparation_time_end;
+
+	u64 load_time_start;
+	u64 load_time_end;
+
+	u64 save_time_start;
+	u64 save_time_end;
+
+	u64 set_pages_overhead_time_start;
+	u64 set_pages_overhead_time_end;
+
+	u64 unmap_pages_overhead_time_start;
+	u64 unmap_pages_overhead_time_end;
+
+
+};
+
+struct status_flags
+{
+	u32 accel_direct_0_occupied_pid;
+	u32 accel_direct_1_occupied_pid;
+
+	u32 accel_indirect_0_occupied_pid;
+	u32 accel_indirect_1_occupied_pid;
+	u32 accel_indirect_2_occupied_pid;
+	u32 accel_indirect_3_occupied_pid;
+
+	u32 accel_sg_0_occupied_pid;
+
+
+	u32 accelerator_busy;
+	u32 open_modules;
+};
+
+struct shared_repository
+{
+	struct metrics unused_shared_metrics;
+
+	struct metrics accel_direct_0_shared_metrics;
+	struct metrics accel_direct_1_shared_metrics;
+
+	struct metrics accel_indirect_0_shared_metrics;
+	struct metrics accel_indirect_1_shared_metrics;
+	struct metrics accel_indirect_2_shared_metrics;
+	struct metrics accel_indirect_3_shared_metrics;
+
+	struct metrics accel_sg_0_shared_metrics;
+
+	struct status_flags shared_status_flags;
+
+};