23 lines
1.1 KiB
Tcl
23 lines
1.1 KiB
Tcl
#--------------------------------------------------------------------------------
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#Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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#--------------------------------------------------------------------------------
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#Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
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#Date : 2025
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#--------------------------------------------------------------------------------
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set_property IOSTANDARD LVCMOS18 [get_ports perst]
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set_property PULLUP true [get_ports perst]
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set_property LOC AV35 [get_ports perst]
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#PCIe Reference Clock (Differential) Ports
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set_property PACKAGE_PIN K8 [get_ports REFCLK_p]
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set_property PACKAGE_PIN K7 [get_ports REFCLK_n]
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#DDR3 Initial Calibration Complete Led Indication Output Port
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set_property PACKAGE_PIN AN39 [get_ports init_calib_complete]
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set_property IOSTANDARD LVCMOS18 [get_ports init_calib_complete]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets pcie_acceleration_vc707_design_i/clocking_wizard/inst/clk_in1_pcie_acceleration_vc707_design_clk_wiz_1_0]
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set_property LOC IBUFDS_GTE2_X1Y5 [get_cells refclk_ibuf]
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