50 lines
2.5 KiB
Tcl
50 lines
2.5 KiB
Tcl
##################################################################################
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# #
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# This Script #
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# 1.Creates a New Vivado Project #
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# 2.Generates the Block Design Described in "pcie_acceleration_vc707_design.tcl" #
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# 3.Imports the Required Constraint File "constraints.xdc" #
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# 4.Imports the Required HDL Wrapper File "hdl_wrapper.v" #
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# #
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##################################################################################
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set relative_directory [pwd]
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set project_directory $relative_directory/pcie_acceleration_vc707
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set ip_repository $relative_directory/Vivado_HLS_IPs
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set constraints_directory $relative_directory/Constraints
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set hdl_wrapper_directory $relative_directory/HDL_Wrapper
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set block_design_directory $relative_directory/Vivado_Block_Design
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set src_bd_design_directory $relative_directory/pcie_acceleration_vc707/pcie_acceleration_vc707.srcs/sources_1/bd/pcie_acceleration_vc707_design
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#Create a New Project Named "pcie_accel_demo"
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create_project pcie_accel_demo $project_directory -part xc7vx485tffg1761-2
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#Set the Board Part which is Required for Certain Configurations such as the Uartlite Controller (RS-232)
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set_property board_part xilinx.com:vc707:part0:1.2 [current_project]
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#Add the HLS IPs before Opening the Block Design
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set_property ip_repo_paths {Vivado_HLS_IPs/Acceleration_Scheduler_Direct Vivado_HLS_IPs/Acceleration_Scheduler_Indirect Vivado_HLS_IPs/Acceleration_Scheduler_SG_XDMA Vivado_HLS_IPs/DMA_SG_PCIe_Scheduler Vivado_HLS_IPs/Fetch_Scheduler Vivado_HLS_IPs/Interrupt_Manager Vivado_HLS_IPs/Info_Memory_Block Vivado_HLS_IPs/Send_Scheduler Vivado_HLS_IPs/Sobel_Filter} [current_project]
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update_ip_catalog
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#Add the Block Design
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source $block_design_directory/pcie_acceleration_vc707_design.tcl
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#Add Constraint Files
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add_files -fileset constrs_1 -norecurse $constraints_directory/constraints.xdc
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import_files -fileset constrs_1 $constraints_directory/constraints.xdc
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#Add the HDL Wrapper
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add_files -norecurse -scan_for_includes $hdl_wrapper_directory/hdl_wrapper.v
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import_files -norecurse $hdl_wrapper_directory/hdl_wrapper.v
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update_compile_order -fileset sources_1
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update_compile_order -fileset sources_1
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update_compile_order -fileset sim_1
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