552 lines
19 KiB
C
552 lines
19 KiB
C
/**
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*
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* This Header File Contains the Necessary Macros for the Kernel Driver Module and the Userspace Application
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*
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*/
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//---Valid Macros To Keep---------------------------------------------//
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#define KC705_PCI_VENDOR_ID 0x10EE
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#define KC705_PCI_DEVICE_ID 0x7021
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#define VC707_PCI_VENDOR_ID 0x10EE
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#define VC707_PCI_DEVICE_ID 0x7022
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#define VENDOR_ID VC707_PCI_VENDOR_ID
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#define DEVICE_ID VC707_PCI_DEVICE_ID
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#define HAVE_REGION 0x01 // I/O Memory region
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#define HAVE_IRQ 0x02 // Interupt
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#define HAVE_KREG 0x04 // Kernel Registration
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#define HAVE_DEBUGFS 0x08 // Debugfs File Creation
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#define DEFAULT_SIGNAL_0 34
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#define DEFAULT_SIGNAL_1 35
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#define DEFAULT_SIGNAL_2 36
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#define DEFAULT_SIGNAL_3 37
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#define DEFAULT_SIGNAL_4 38
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#define DEFAULT_SIGNAL_5 39
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#define DEFAULT_SIGNAL_6 40
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#define DEFAULT_SIGNAL_SG 41
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#define OCCUPIED 1
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#define NOT_OCCUPIED 0
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/**
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* @note
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*
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* The Following Macro Line Works as a Switch.
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* Remove/Add One of the '*' at the Beggining to Change the State of the Switch.
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* One '*' Enables --> BEST_AVAILABLE.
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* Two '*' Enable --> GREEDY.
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* This is Used to Safely Disable/Enable Specific Code Parts of the Driver.
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*/
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/*/ #define BEST_AVAILABLE /*/ #define GREEDY /**/
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/** @note
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*
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* The Macros Below are Used to Enable/Disable Debug Messages.
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*
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* The DEBUG_MESSAGES is Used to Print the Driver's Debug Messages to the /var/log/kern.log File.
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* The DEBUG_MESSAGES_UI is Used to Print the Userspace Application's Debug messages to the Terminal.
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*
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* Uncomment to Enable the Messages Debugging.
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*/
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//#define DEBUG_MESSAGES
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//#define DEBUG_MESSAGES_UI
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#define SUCCESS 0
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#define FAILURE 1
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#define BYTE 1
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#define KBYTE 1024
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#define MBYTE 1048576
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#define START 0x1
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#define ACK 0x1
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#define MMAP_ALLOCATION_SIZE 4 * MBYTE
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#define POSIX_ALLOCATED_SIZE 32 * MBYTE
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#define KERNEL_ALLOCATION_SIZE 4 * MBYTE
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#define OPERATION_START_TIMER 0x18000000
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#define BAR0_32BIT 0 //For 32 Bit Addressing
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#define BAR1_32BIT 1 //For 32 Bit Addressing
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#define BAR2_32BIT 2 //For 32 Bit Addressing
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#define BAR3_32BIT 3 //For 32 Bit Addressing
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#define BAR4_32BIT 4 //For 32 Bit Addressing
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#define BAR5_32BIT 5 //For 32 Bit Addressing
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#define BAR0_64BIT 0 //For 64 Bit Addressing
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#define BAR1_64BIT 2 //For 64 Bit Addressing
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#define BAR2_64BIT 4 //For 64 Bit Addressing
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#define ACCELERATOR_DIRECT_0_OCCUPIED 0x01
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#define ACCELERATOR_DIRECT_1_OCCUPIED 0x02
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#define ACCELERATOR_INDIRECT_0_OCCUPIED 0x04
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#define ACCELERATOR_INDIRECT_1_OCCUPIED 0x08
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#define ACCELERATOR_INDIRECT_2_OCCUPIED 0x10
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#define ACCELERATOR_INDIRECT_3_OCCUPIED 0x20
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#define ACCELERATOR_SG_OCCUPIED 0x40
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#define ACCELERATOR_ALL_OCCUPIED 0x3F
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#define ACCELERATOR_NO_OCCUPIED 0x00
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#define ENABLE_GCC_MC 0x00010001 //Enable Global Clock Counter and Metrics Counter Mask
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#define RESET_GCC_MC 0x00020002 //Reset Global Clock Counter and Metrics Counter Mask
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#define APM_CR_OFFSET 0x300 //AXI Performance Monitor Control Register Offset(0x60 for Long Int Offset 0x300 for Byte Offset)
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#define APM_GCC_LOWER_OFFSET 0X0004 //Global Clock Counter Lower 32Bits Register
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#define APM_GCC_UPPER_OFFSET 0X0000 //Global Clock Counter Upper 32Bits Register
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#define METRIC_SELECTOR_REGISTER_0_OFFSET 0X0044
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#define METRIC_SELECTOR_REGISTER_1_OFFSET 0X0048
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#define METRIC_SELECTOR_REGISTER_2_OFFSET 0X004C
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//////////////////////////////////////////////////////////////////////////////////////
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// PCIe BAR0 Address Space -Mapping the FPGA AXI Address Space (HW Peripherals)
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//////////////////////////////////////////////////////////////////////////////////////
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#define BAR0_OFFSET_INTERRUPT_CONTROLLER 0x00020000
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#define BAR0_OFFSET_UARTLITE 0x00010000
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#define BAR0_OFFSET_PCIE_CTL 0x00020000
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#define BAR0_OFFSET_GPIO_PCIE_INTERRUPT 0x00030000
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#define BAR0_OFFSET_GPIO_MSI 0x00040000
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#define BAR0_OFFSET_TIMER 0x00050000
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#define BAR0_OFFSET_FETCH_SCHEDULER 0x00060000
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#define BAR0_OFFSET_SEND_SCHEDULER 0x00070000
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#define BAR0_OFFSET_SCHEDULER_BUFFER_FETCH 0x00080000
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#define BAR0_OFFSET_SCHEDULER_BUFFER_SEND 0x00090000
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#define BAR0_OFFSET_CDMA_FETCH 0x000A0000
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#define BAR0_OFFSET_CDMA_SEND 0x000B0000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_0_ACCELERATION_SCHEDULER_DIRECT 0x000C0000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_0_APM 0x000D0000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_0_DMA 0x000E0000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_0_SOBEL_FILTER 0x000F0000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_1_ACCELERATION_SCHEDULER_DIRECT 0x00100000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_1_APM 0x00110000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_1_DMA 0x00120000
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#define BAR0_OFFSET_ACCEL_GROUP_DIRECT_1_SOBEL_FILTER 0x00130000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_0_ACCELERATION_SCHEDULER_INDIRECT 0x00140000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_0_APM 0x00150000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_0_DMA 0x00160000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_0_SOBEL_FILTER 0x00170000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_1_ACCELERATION_SCHEDULER_INDIRECT 0x00180000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_1_APM 0x00190000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_1_DMA 0x001A0000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_1_SOBEL_FILTER 0x001B0000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_2_ACCELERATION_SCHEDULER_INDIRECT 0x001C0000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_2_APM 0x001D0000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_2_DMA 0x001E0000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_2_SOBEL_FILTER 0x001F0000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_3_ACCELERATION_SCHEDULER_INDIRECT 0x00200000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_3_APM 0x00210000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_3_DMA 0x00220000
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#define BAR0_OFFSET_ACCEL_GROUP_INDIRECT_3_SOBEL_FILTER 0x00230000
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#define BAR0_OFFSET_ACCEL_GROUP_SG_ACCELERATION_SCHEDULER_SG 0x00240000
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#define BAR0_OFFSET_ACCEL_GROUP_SG_APM 0x00250000
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#define BAR0_OFFSET_ACCEL_GROUP_SG_DMA_SG_PCIE_SCHEDULER 0x00260000
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#define BAR0_OFFSET_ACCEL_GROUP_SG_SOBEL_FILTER_4K 0x00280000
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#define BAR0_OFFSET_ACCEL_GROUP_SG_DMA 0x00290000
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#define BAR0_OFFSET_GPIO_MSI_READ 0x00300000
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#define BAR0_OFFSET_INTERRUPT_MANAGER 0x00310000
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#define BAR0_OFFSET_GPIO_ACK 0x00320000
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//////////////////////////////////////////////////////////////////////////////////////
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// Acceleration Scheduler Direct Register Offsets
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//////////////////////////////////////////////////////////////////////////////////////
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#define ACCELERATION_SCHEDULER_DIRECT_CONTROL_REGISTER_OFFSET 0X00
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#define ACCELERATION_SCHEDULER_DIRECT_GIE_REGISTER_OFFSET 0X04
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#define ACCELERATION_SCHEDULER_DIRECT_IER_REGISTER_OFFSET 0X08
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#define ACCELERATION_SCHEDULER_DIRECT_ISR_REGISTER_OFFSET 0X0C
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#define ACCELERATION_SCHEDULER_DIRECT_DMA_DEVICE_BASE_ADDRESS_REGISTER_OFFSET 0X18
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#define ACCELERATION_SCHEDULER_DIRECT_SOBEL_DEVICE_BASE_ADDRESS_REGISTER_OFFSET 0X20
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#define ACCELERATION_SCHEDULER_DIRECT_GPIO_DEVICE_BASE_ADDRESS_REGISTER_OFFSET 0X28
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#define ACCELERATION_SCHEDULER_DIRECT_APM_DEVICE_BASE_ADDRESS_REGISTER_OFFSET 0X30
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#define ACCELERATION_SCHEDULER_DIRECT_SHARED_APM_DEVICE_BASE_ADDRESS_REGISTER_OFFSET 0X38
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#define ACCELERATION_SCHEDULER_DIRECT_SHARED_METRICS_DEVICE_BASE_ADDRESS_REGISTER_OFFSET 0X40
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#define ACCELERATION_SCHEDULER_DIRECT_IMAGE_COLUMNS_REGISTER_OFFSET 0X48
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#define ACCELERATION_SCHEDULER_DIRECT_IMAGE_ROWS_REGISTER_OFFSET 0X50
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#define ACCELERATION_SCHEDULER_DIRECT_HOST_SOURCE_ADDRESS_REGISTER_OFFSET 0X58
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#define ACCELERATION_SCHEDULER_DIRECT_HOST_DESTINATION_ADDRESS_REGISTER_OFFSET 0X60
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#define ACCELERATION_SCHEDULER_DIRECT_INITIATOR_GROUP_REGISTER_OFFSET 0X68
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//////////////////////////////////////////////////////////////////////////////////////
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// Acceleration Scheduler Indirect Register Offsets
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//////////////////////////////////////////////////////////////////////////////////////
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#define ACCELERATION_SCHEDULER_INDIRECT_CONTROL_REGISTER_OFFSET 0x00
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#define ACCELERATION_SCHEDULER_INDIRECT_GIE_REGISTER_OFFSET 0x04
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#define ACCELERATION_SCHEDULER_INDIRECT_IER_REGISTER_OFFSET 0x08
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#define ACCELERATION_SCHEDULER_INDIRECT_ISR_REGISTER_OFFSET 0x0C
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#define ACCELERATION_SCHEDULER_INDIRECT_SCHEDULER_BUFFER_BASE_ADDRESS_FETCH_REGISTER_OFFSET 0x18
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#define ACCELERATION_SCHEDULER_INDIRECT_SOURCE_ADDRESS_REG_FETCH_REGISTER_OFFSET 0x20
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#define ACCELERATION_SCHEDULER_INDIRECT_DESTINATION_ADDRESS_REG_FETCH_REGISTER_OFFSET 0x28
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#define ACCELERATION_SCHEDULER_INDIRECT_DATA_SIZE_REG_FETCH_REGISTER_OFFSET 0x30
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#define ACCELERATION_SCHEDULER_INDIRECT_OFFSET_REG__FETCH__REGISTER_OFFSET 0x38
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#define ACCELERATION_SCHEDULER_INDIRECT_SOURCE_ADDRESS_FETCH_REGISTER_OFFSET 0x40
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#define ACCELERATION_SCHEDULER_INDIRECT_DESTINATION_ADDRESS_FETCH_REGISTER_OFFSET 0x48
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#define ACCELERATION_SCHEDULER_INDIRECT_OFFSET_FETCH_REGISTER_OFFSET 0x50
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#define ACCELERATION_SCHEDULER_INDIRECT_SCHEDULER_BUFFER_BASE_ADDRESS_SEND_REGISTER_OFFSET 0x58
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#define ACCELERATION_SCHEDULER_INDIRECT_SOURCE_ADDRESS_REG_SEND_REGISTER_OFFSET 0x60
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#define ACCELERATION_SCHEDULER_INDIRECT_DESTINATION_ADDRESS_REG_SEND_REGISTER_OFFSET 0x68
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#define ACCELERATION_SCHEDULER_INDIRECT_DATA_SIZE_REG_SEND_REGISTER_OFFSET 0x70
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#define ACCELERATION_SCHEDULER_INDIRECT_OFFSET_REG__SEND_REGISTER_OFFSET 0x78
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#define ACCELERATION_SCHEDULER_INDIRECT_SOURCE_ADDRESS_SEND_REGISTER_OFFSET 0x80
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#define ACCELERATION_SCHEDULER_INDIRECT_DESTINATION_ADDRESS_SEND_REGISTER_OFFSET 0x88
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#define ACCELERATION_SCHEDULER_INDIRECT_OFFSET_SEND_REGISTER_OFFSET 0x90
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#define ACCELERATION_SCHEDULER_INDIRECT_DMA_BASE_ADDRESS_REGISTER_OFFSET 0x98
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#define ACCELERATION_SCHEDULER_INDIRECT_SOBEL_BASE_ADDRESS_REGISTER_OFFSET 0xA0
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#define ACCELERATION_SCHEDULER_INDIRECT_IMAGE_COLUMNS_REGISTER_OFFSET 0xA8
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#define ACCELERATION_SCHEDULER_INDIRECT_IMAGE_ROWS_REGISTER_OFFSET 0xB0
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#define ACCELERATION_SCHEDULER_INDIRECT_ACCEL_GROUP_REGISTER_OFFSET 0xB8
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#define ACCELERATION_SCHEDULER_INDIRECT_SHARED_APM_BASE_ADDRESS_REGISTER_OFFSET 0xC0
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#define ACCELERATION_SCHEDULER_INDIRECT_SHARED_METRICS_BASE_ADDRESS_REGISTER_OFFSET 0xC8
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#define ACCELERATION_SCHEDULER_INDIRECT_APM_BASE_ADDRESS_REGISTER_OFFSET 0xD0
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//////////////////////////////////////////////////////////////////////////////////////
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// Acceleration Scheduler SG Register Offsets
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//////////////////////////////////////////////////////////////////////////////////////
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_AP_CTRL 0x00
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_GIE 0x04
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_IER 0x08
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_ISR 0x0c
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_AP_RETURN 0x10
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_DMA_SG_PCIE_SCHEDULER_BASE_ADDRESS_DATA 0x18
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_SOBEL_DEVICE_ADDRESS_DATA 0x20
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_GPIO_DEVICE_ADDRESS_DATA 0x28
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_APM_DEVICE_ADDRESS_DATA 0x30
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_SHARED_APM_DEVICE_ADDRESS_DATA 0x38
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_SHARED_METRICS_ADDRESS_DATA 0x40
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_IMAGE_COLS_DATA 0x48
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_IMAGE_ROWS_DATA 0x50
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#define XACCELERATION_SCHEDULER_SG_XDMA_CFG_ADDR_ACCEL_GROUP_DATA 0x58
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//////////////////////////////////////////////////////////////////////////////////////
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// AXI BARs Offsets
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//////////////////////////////////////////////////////////////////////////////////////
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#define AXI_BAR_0_OFFSET 0x20000000
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#define AXI_BAR_1_OFFSET 0x30000000
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#define AXI_BAR_2_OFFSET 0x40000000
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#define AXI_BAR_3_OFFSET 0x50000000
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#define AXI_BAR_4_OFFSET 0x60000000
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#define AXI_BAR_5_OFFSET 0x70000000
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//////////////////////////////////////////////////////////////////////////////////////
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// AXI BARs Dynamic Address Translation Registers Offsets
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//////////////////////////////////////////////////////////////////////////////////////
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#define AXI_BAR0_LOWER_ADDRESS_OFFSET 0x20C
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#define AXI_BAR0_UPPER_ADDRESS_OFFSET 0x208
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#define AXI_BAR1_LOWER_ADDRESS_OFFSET 0x214
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#define AXI_BAR1_UPPER_ADDRESS_OFFSET 0x210
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#define AXI_BAR2_LOWER_ADDRESS_OFFSET 0x21C
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#define AXI_BAR2_UPPER_ADDRESS_OFFSET 0x218
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#define AXI_BAR3_LOWER_ADDRESS_OFFSET 0x224
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#define AXI_BAR3_UPPER_ADDRESS_OFFSET 0x220
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#define AXI_BAR4_LOWER_ADDRESS_OFFSET 0x22C
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#define AXI_BAR4_UPPER_ADDRESS_OFFSET 0x228
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#define AXI_BAR5_LOWER_ADDRESS_OFFSET 0x234
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#define AXI_BAR5_UPPER_ADDRESS_OFFSET 0x230
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//////////////////////////////////////////////////////////////////////////////////////
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// IOCtl Commands
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//////////////////////////////////////////////////////////////////////////////////////
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#define COMMAND_REQUEST_ACCELERATOR_ACCESS 0x0100
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#define COMMAND_REQUEST_ACCELERATOR_SG_ACCESS 0x0200
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#define COMMAND_SET_PAGES 0x0300
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#define COMMAND_UNMAP_PAGES 0x0400
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#define COMMAND_RESET_VARIABLES 0x0500
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//////////////////////////////////////////////////////////////////////////////////////
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// Scenarios
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//////////////////////////////////////////////////////////////////////////////////////
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#define SCENARIO_SCATTER_GATHER 1
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#define SCENARIO_WORST_CASE 2
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#define SCENARIO_WORST_CASE_CDMA 3
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struct image_info
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{
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uint32_t rows;
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uint32_t columns;
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uint64_t size;
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};
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struct metrics
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{
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/*
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* AXI Performance Monitor Metrics
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*/
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uint32_t apm_read_transactions; //Offset 0 Bytes
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uint32_t apm_read_bytes; //Offset 4 Bytes
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uint32_t apm_write_transactions; //Offset 8 Bytes
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uint32_t apm_write_bytes; //Offset 12 Bytes
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uint32_t apm_packets; //Offset 16 Bytes
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uint32_t apm_bytes; //Offset 20 Bytes
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uint32_t apm_gcc_l; //Offset 24 Bytes
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uint32_t apm_gcc_u; //Offset 28 Bytes
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uint32_t cdma_fetch_time_start_l; //Offset 32 Bytes
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uint32_t cdma_fetch_time_start_u; //Offset 36 Bytes
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uint32_t cdma_fetch_time_end_l; //Offset 40 Bytes
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uint32_t cdma_fetch_time_end_u; //Offset 44 Bytes
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uint32_t cdma_send_time_start_l; //Offset 48 Bytes
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uint32_t cdma_send_time_start_u; //Offset 52 Bytes
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uint32_t cdma_send_time_end_l; //Offset 56 Bytes
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uint32_t cdma_send_time_end_u; //Offset 60 Bytes
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uint32_t dma_accel_time_start_l; //Offset 64 Bytes
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uint32_t dma_accel_time_start_u; //Offset 68 Bytes
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uint32_t dma_accel_time_end_l; //Offset 72 Bytes
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uint32_t dma_accel_time_end_u; //Offset 76 Bytes
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struct image_info shared_image_info; // Offset 80 Bytes
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/*
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* Kernel and Userspace Metrics
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*/
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uint64_t total_time_start;
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uint64_t total_time_end;
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uint64_t sleep_time_start;
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uint64_t sleep_time_end;
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uint64_t preparation_time_start;
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uint64_t preparation_time_end;
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uint64_t load_time_start;
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uint64_t load_time_end;
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uint64_t save_time_start;
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uint64_t save_time_end;
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};
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struct metrics_per_process
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{
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struct metrics agd0;
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struct metrics agd1;
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struct metrics agi0;
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struct metrics agi1;
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struct metrics agi2;
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struct metrics agi3;
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struct metrics agsg;
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/*
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* Kernel and Userspace Metrics
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*/
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uint64_t total_time_start;
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uint64_t total_time_end;
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uint64_t sleep_time_start;
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uint64_t sleep_time_end;
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uint64_t preparation_time_start;
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uint64_t preparation_time_end;
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uint64_t load_time_start;
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uint64_t load_time_end;
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uint64_t save_time_start;
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uint64_t save_time_end;
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uint64_t set_pages_overhead_time_start;
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uint64_t set_pages_overhead_time_end;
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uint64_t unmap_pages_overhead_time_start;
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uint64_t unmap_pages_overhead_time_end;
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};
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struct status_flags
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{
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uint32_t accel_direct_0_occupied_pid;
|
|
|
|
uint32_t accel_direct_1_occupied_pid;
|
|
|
|
uint32_t accel_indirect_0_occupied_pid;
|
|
|
|
uint32_t accel_indirect_1_occupied_pid;
|
|
|
|
uint32_t accel_indirect_2_occupied_pid;
|
|
|
|
uint32_t accel_indirect_3_occupied_pid;
|
|
|
|
uint32_t accel_sg_0_occupied_pid;
|
|
|
|
|
|
uint32_t accelerator_busy;
|
|
uint32_t open_modules;
|
|
|
|
uint32_t agd0_busy;
|
|
uint32_t agd1_busy;
|
|
uint32_t agi0_busy;
|
|
uint32_t agi1_busy;
|
|
uint32_t agi2_busy;
|
|
uint32_t agi3_busy;
|
|
uint32_t agsg_busy;
|
|
|
|
};
|
|
|
|
struct shared_repository
|
|
{
|
|
struct metrics unused_shared_metrics;
|
|
struct metrics accel_direct_0_shared_metrics;
|
|
struct metrics accel_direct_1_shared_metrics;
|
|
|
|
struct metrics accel_indirect_0_shared_metrics;
|
|
struct metrics accel_indirect_1_shared_metrics;
|
|
struct metrics accel_indirect_2_shared_metrics;
|
|
struct metrics accel_indirect_3_shared_metrics;
|
|
|
|
struct metrics accel_sg_0_shared_metrics;
|
|
|
|
struct status_flags shared_status_flags;
|
|
|
|
};
|
|
|
|
struct shared_repository_process
|
|
{
|
|
struct metrics_per_process process_metrics;
|
|
struct image_info shared_image_info;
|
|
int accel_completed;
|
|
int accel_occupied;
|
|
int image_segments;
|
|
|
|
};
|
|
|
|
typedef struct {
|
|
uint8_t magic[2];
|
|
} bmpfile_magic_t;
|
|
|
|
typedef struct {
|
|
uint32_t filesz;
|
|
uint16_t creator1;
|
|
uint16_t creator2;
|
|
uint32_t bmp_offset;
|
|
} bmpfile_header_t;
|
|
|
|
typedef struct {
|
|
uint32_t header_sz;
|
|
int32_t width;
|
|
int32_t height;
|
|
uint16_t nplanes;
|
|
uint16_t bitspp;
|
|
uint32_t compress_type;
|
|
uint32_t bmp_bytesz;
|
|
int32_t hres;
|
|
int32_t vres;
|
|
uint32_t ncolors;
|
|
uint32_t nimpcolors;
|
|
} bitmap_info_header_t;
|
|
|
|
|
|
typedef struct {
|
|
uint8_t b;
|
|
uint8_t g;
|
|
uint8_t r;
|
|
uint8_t nothing;
|
|
} rgb_t;
|
|
|
|
|
|
typedef unsigned char pixel_t;
|
|
|
|
|
|
struct pid_reserved_memories {
|
|
|
|
pid_t pid;
|
|
|
|
struct shared_repository_process *shared_repo_virtual_address;
|
|
uint32_t shared_repo_physical_address;
|
|
|
|
uint64_t *pre_process_mmap_virtual_address;
|
|
uint32_t pre_process_mmap_physical_address;
|
|
|
|
uint64_t *post_process_mmap_virtual_address;
|
|
uint32_t post_process_mmap_physical_address;
|
|
|
|
struct sg_table *dma_sg_table_source;
|
|
struct scatterlist *scatterlist_pointer_source;
|
|
|
|
int buffer_dma_buffers_source;
|
|
|
|
int buffer_mapped_pages_source;
|
|
|
|
|
|
struct sg_table *dma_sg_table_destination;
|
|
struct scatterlist *scatterlist_pointer_destination;
|
|
|
|
int buffer_dma_buffers_destination;
|
|
|
|
int buffer_mapped_pages_destination;
|
|
|
|
uint64_t *u64_sg_list_source;
|
|
uint64_t *u64_sg_list_destination;
|
|
|
|
struct pid_reserved_memories *next_pid;
|
|
|
|
};
|
|
|
|
struct sg_list_addresses
|
|
{
|
|
pid_t current_pid;
|
|
|
|
uint64_t *sg_list_source_address;
|
|
uint64_t *sg_list_destination_address;
|
|
|
|
};
|
|
|
|
struct per_thread_info
|
|
{
|
|
struct shared_repository_process *shared_repo_kernel_address;
|
|
uint8_t *u8_pre_process_kernel_address;
|
|
uint8_t *u8_post_process_kernel_address;
|
|
|
|
int pre_process_mmap_file;
|
|
int post_process_mmap_file;
|
|
int shared_repo_mmap_file;
|
|
};
|