129 lines
3.7 KiB
Verilog
129 lines
3.7 KiB
Verilog
//--------------------------------------------------------------------------------
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//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
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//Date : 2025
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module pcie_acceleration_vc707_design_wrapper
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(REFCLK_p,
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REFCLK_n,
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ddr3_sdram_addr,
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ddr3_sdram_ba,
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ddr3_sdram_cas_n,
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ddr3_sdram_ck_n,
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ddr3_sdram_ck_p,
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ddr3_sdram_cke,
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ddr3_sdram_cs_n,
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ddr3_sdram_dm,
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ddr3_sdram_dq,
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ddr3_sdram_dqs_n,
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ddr3_sdram_dqs_p,
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ddr3_sdram_odt,
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ddr3_sdram_ras_n,
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ddr3_sdram_reset_n,
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ddr3_sdram_we_n,
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init_calib_complete,
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pcie_7x_mgt_rxn,
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pcie_7x_mgt_rxp,
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pcie_7x_mgt_txn,
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pcie_7x_mgt_txp,
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perst,
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reset,
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rs232_uart_rxd,
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rs232_uart_txd,
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sys_diff_clock_clk_n,
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sys_diff_clock_clk_p);
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input REFCLK_p;
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input REFCLK_n;
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output [13:0]ddr3_sdram_addr;
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output [2:0]ddr3_sdram_ba;
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output ddr3_sdram_cas_n;
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output [0:0]ddr3_sdram_ck_n;
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output [0:0]ddr3_sdram_ck_p;
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output [0:0]ddr3_sdram_cke;
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output [0:0]ddr3_sdram_cs_n;
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output [7:0]ddr3_sdram_dm;
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inout [63:0]ddr3_sdram_dq;
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inout [7:0]ddr3_sdram_dqs_n;
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inout [7:0]ddr3_sdram_dqs_p;
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output [0:0]ddr3_sdram_odt;
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output ddr3_sdram_ras_n;
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output ddr3_sdram_reset_n;
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output ddr3_sdram_we_n;
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output init_calib_complete;
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input [3:0]pcie_7x_mgt_rxn;
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input [3:0]pcie_7x_mgt_rxp;
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output [3:0]pcie_7x_mgt_txn;
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output [3:0]pcie_7x_mgt_txp;
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input perst;
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input reset;
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input rs232_uart_rxd;
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output rs232_uart_txd;
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input sys_diff_clock_clk_n;
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input sys_diff_clock_clk_p;
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wire REFCLK_p;
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wire REFCLK_n;
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wire [13:0]ddr3_sdram_addr;
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wire [2:0]ddr3_sdram_ba;
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wire ddr3_sdram_cas_n;
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wire [0:0]ddr3_sdram_ck_n;
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wire [0:0]ddr3_sdram_ck_p;
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wire [0:0]ddr3_sdram_cke;
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wire [0:0]ddr3_sdram_cs_n;
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wire [7:0]ddr3_sdram_dm;
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wire [63:0]ddr3_sdram_dq;
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wire [7:0]ddr3_sdram_dqs_n;
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wire [7:0]ddr3_sdram_dqs_p;
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wire [0:0]ddr3_sdram_odt;
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wire ddr3_sdram_ras_n;
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wire ddr3_sdram_reset_n;
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wire ddr3_sdram_we_n;
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wire init_calib_complete;
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wire [3:0]pcie_7x_mgt_rxn;
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wire [3:0]pcie_7x_mgt_rxp;
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wire [3:0]pcie_7x_mgt_txn;
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wire [3:0]pcie_7x_mgt_txp;
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wire perst;
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wire reset;
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wire rs232_uart_rxd;
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wire rs232_uart_txd;
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wire sys_diff_clock_clk_n;
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wire sys_diff_clock_clk_p;
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IBUFDS_GTE2 refclk_ibuf (.O(REFCLK), .ODIV2(), .I(REFCLK_p), .CEB(1'b0), .IB(REFCLK_n));
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pcie_acceleration_vc707_design pcie_acceleration_vc707_design_i
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(.REFCLK(REFCLK),
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.ddr3_sdram_addr(ddr3_sdram_addr),
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.ddr3_sdram_ba(ddr3_sdram_ba),
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.ddr3_sdram_cas_n(ddr3_sdram_cas_n),
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.ddr3_sdram_ck_n(ddr3_sdram_ck_n),
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.ddr3_sdram_ck_p(ddr3_sdram_ck_p),
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.ddr3_sdram_cke(ddr3_sdram_cke),
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.ddr3_sdram_cs_n(ddr3_sdram_cs_n),
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.ddr3_sdram_dm(ddr3_sdram_dm),
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.ddr3_sdram_dq(ddr3_sdram_dq),
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.ddr3_sdram_dqs_n(ddr3_sdram_dqs_n),
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.ddr3_sdram_dqs_p(ddr3_sdram_dqs_p),
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.ddr3_sdram_odt(ddr3_sdram_odt),
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.ddr3_sdram_ras_n(ddr3_sdram_ras_n),
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.ddr3_sdram_reset_n(ddr3_sdram_reset_n),
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.ddr3_sdram_we_n(ddr3_sdram_we_n),
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.init_calib_complete(init_calib_complete),
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.pcie_7x_mgt_rxn(pcie_7x_mgt_rxn),
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.pcie_7x_mgt_rxp(pcie_7x_mgt_rxp),
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.pcie_7x_mgt_txn(pcie_7x_mgt_txn),
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.pcie_7x_mgt_txp(pcie_7x_mgt_txp),
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.perst(perst),
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.reset(reset),
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.rs232_uart_rxd(rs232_uart_rxd),
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.rs232_uart_txd(rs232_uart_txd),
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.sys_diff_clock_clk_n(sys_diff_clock_clk_n),
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.sys_diff_clock_clk_p(sys_diff_clock_clk_p));
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endmodule
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