18 lines
348 B
Tcl
18 lines
348 B
Tcl
open_project Send_Scheduler
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set_top send_scheduler
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add_files send_scheduler.cpp
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open_solution "solution1"
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#The Part Refers to the Xilinx Virtex 7 VC707 FPGA Development Board
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set_part {xc7vx485tffg1761-2}
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create_clock -period 10 -name default
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csynth_design
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export_design -format ip_catalog -display_name "Send Scheduler" -version "3.0"
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exit
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